Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Writing to DDR RAM on Virtex II Pro Board on PLB Bus
My question: How can I write to DDR SDRAM from a custom IP core on the PLB Bus? Background: I am developing a custom IP core for a Virtex II Pro based system (the Xilinx XUP board). This core captures...
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16 years ago
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fpga reset (re-initialize) of spartan3e
Hi, is it possible to force a re initialization from within the fpga ? if I have, for instance. transfered new configuration data to a flash, and want to reinitialize the fpga without using the...
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16 years ago
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System Generator Error
Hi, I am trying to generate the ise project files from the system generator token in simulink but i am getting the following error....
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16 years ago
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Synthesisable Timer in VHDL
hi all: i am currently working on a "toy" design of my first big project (in VHDL) on the Xilinx Spartan III starter kit. now facing a timer problem and i could not properlly solve it using my limited...
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16 years ago
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After reset, the PC register of PPC is not back to 0Xfffffffc
Hi, All, I built a PowerPC system on Xilinx ML410 board (Virtex4 fx60), the system contains 64K OCM instruction memory and 64K PLB data memory. I used XMD to debug the system via the jtagppc, when I...
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16 years ago
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Announcement: Releasing LogicSim 3.3 and WaveProbe 1.1
I'd like to announce the release of LogicSim 3.3 and WaveProbe 1.0. LogicSim is an affordable and user-friendly Verilog simulator for ASIC and FPGA design verification. It offers a powerful and...
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16 years ago
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ISE 10.1 - Initial experience
I've got a fairly large design that I've been working with in ISE 9.2.04 for a while - it takes about 90% of a V2P100 and runs to completion in about 3.5 to 4 hours on my Linux x86_64 system (Athlon...
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16 years ago
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async clk input, clock glitches
Hi FPGA has 1) 50mhz system clock from ext oscillator 2) 4Mhz clk that is async to the 50mhz problem, the 4MHz clk input sees double clk pulse, error rate approximate 1 to 10.000.000 unfortunatly the...
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16 years ago
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Newbies: Answer to "What is an FPGA?" in video
Hi guys, This is one just for FPGA newbies, and possibly also a place where you can point people when they ask you what an FPGA is... Video #2 here answers the question "What is an FPGA?" That video...
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16 years ago
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FPGA beginner video guide, blog comments by Max Maxfield
Hi all, I announced a Getting Started With Xilinx FPGAs Video Guide here a little while ago. Clive (Max) Maxfield has now done a blog on them at Cheers, Anthony
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16 years ago
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Having trouble building an old Xilinx Spartan3 FPGA project I did on ISE 8.2i and EDK8.2 for microblaze. Also have ISE9.2i installed.
I'm trying to rebuild an old project I did on ISE8.2i. I reinstalled 8.2i on my PC. I also have 9.2i installed on the same PC. I don't know if they would conflict or not? My environment variable...
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16 years ago
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Can't read external Flash in a V4 based PPC system through gdb
This is a weird problem. I have a MPMC2 based PPC system with Flash memory attached via opb_emc. The design works fine including the flash memory, which is used for loading FPGA itself amongst other...
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16 years ago
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Webpack 10.1 on 64-bit linux
Congrats to Xilinx on the recent release of ISE 10.1, and thanks for simultaneously releasing WebPack along with ISE Foundation. But... it appears the hoops necessary to get the 32-bit webpack working...
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16 years ago
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quick question
what does the following code do output
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16 years ago
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ISE 10.1 XST runs in background?
Hi, I installed ISE 10.1 the other day and just tried it out for the first time this morning. I run my synthesis jobs on a Linux x86_64 machine and use home-made make scripts to manage the build...
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16 years ago
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