Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Examples for Spartan3 StarterKit
Hi, I'm currently developing some examples for the Spartan3 StarterKit from digilent. Maybe this is interesting for newbies. I know that they are not spectacular at the moment. You can leave me a...
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16 years ago
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Xilinx FPGA + SMPS
Is there any known pitfalls or problems with driving xilinx fpga (spartan) with smps (buck) ..?
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16 years ago
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One more question. WebPACK key with ISE
One more question. For example, I have no WebPACK distributive but I have ISE Foundation distributive. May I use ISE Foundation distributive but enter WebPACK key at installation? Do I have to...
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16 years ago
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loop back on a MARVELL switch
Hi all, I have a marvell switched based system with two ports. I want to loop back packets that i send on this switch. Could anyone suggest me how to do this. thanks
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16 years ago
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Downloading some data from flash memory thru JTAG.
Hi. I have common configuration scheme for Altera Stratix II: flash memory + Max device + Stratix II. Flash memory configured by FPP method thru JTAG. Is there any simple method to download flash...
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16 years ago
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problem with synthesis
The following module generates this error: The logic for does not match a known FF or Latch template. The logic for does not match a known FF or Latch template. What I want to do is to have a module...
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16 years ago
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synplify pro generates negative slack
SRLen7 : SRL16 -- synthesis translate_off generic map( INIT => x"0000") -- synthesis translate_on port map (Q => enadd5_d4, A0 => '1', A1 => '1', A2 => '0', A3 => '0', CLK => clock, D => enadd5);...
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16 years ago
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No synchronization word in prom file (XILINX)?
I tried to reflash my SPI FLASH memory with the DOS program supplied by XILINX (I don't remember the name of the DOS program) and get an error saying the synchronization word is missing. How can I...
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16 years ago
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Spartan3 JTAG flash In System Programming over Ethernet
I am interested in using the Xilinx 10/100 Ethernet solution supported in their Spartan3 eveluation kit. I have a JTAG based flash PROM XCF02S connected to the Spartan3. I would like to know best way...
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16 years ago
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Beginner's silly question about ICAP
Hi Comrade, I run into troubles trying to read anything using ICAP. I set "-g security:none", just in case. When I try to read for example STAT Register, BUSY goes HIGH when I switch to reading and...
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16 years ago
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Protecting design from being downloaded on other (similar) FPGA devices
Hi, I need to know how can I prohibit a configuration file from being downloaded on a similar FPGA device. For example, if I have two similar FPGA boards and I want only one FPGA board to be...
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16 years ago
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EDK 10.1 first impressions
Hi here it goes: I got last week new notebook that is faster then the desktop, so I installed 10.x tools there. And I had a small task to verify something with ML505, so I fire up EDK 10.1 open the...
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16 years ago
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Conterfeit parts guidance
Hello all, I am a Quality manager at Xilinx, and I have asked to provide specific guidance on the question of counterfieting. I would like to start by saying that the ONLY way to protect yourself is...
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16 years ago
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ModelSim XE problems with a VHDL coregen in a Virtex 5
I'm getting a fatal error when I try and simulate a Virtex 5 VHDL project with a block memory core built with coregen. The Virtex 5 Coregen is only allowing Block Memory Generator V2.6 to be used. I...
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16 years ago
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Xilinx ISE 10.1 Ubuntu Linux Installation - Driver Installation Problem
I installed the 10.1 ISE Webpack. The pack installed successfully except for the driver. I have found( that in 10.1 the driver is prepackaged. I enabled the environment variable(XIL_IMPACT_USE_LIBUSB...
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16 years ago
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