100 Mbit manchester coded signal in FPGA

Michael,

The use of a CPLD or FPGA inversion is not recommended for a crystal oscillator.

The problem is not that it won't work (it often does), it is that it sometimes will not start. The inversion also comes with a delay that is not something that you can easily model and prove that the oscillator will always start up.

Once started, it will oscillate, it is the starting that is sometimes difficult,

Aust> Hi all,

No, I don't think this will work. You need an unbuffered inverter, don't think the CPLD will have this.

Yep, that works. I've recovered RZ data with a 4 times clock, same thing applies to Manchester coding, so you'd be able to do it with a 200MHz clock on the DDR IOB input registers. Check out XAPP224. HTH, Syms.

Michael Dreschmann schrieb:

you can look at the USB DPLL get the sub phy from opencores as example it uses 4x clock to deliver mid-bit clock enable to latch the data. something similar should work for manchester as well.

cpld oscillator shure work, but you still need a resistor across not gate in-out it want oscillate otherwise. I have spent some time trying to get an crystal to swing on FPGA pins without external resistor but have not yet succeeded.

Antti

"Austin Lesea" schrieb im Newsbeitrag news: snipped-for-privacy@xilinx.com...

hm you mean that an CPLD/FPGA NOT gate with 1 (or 2 resistors) and 2 caps and crystal will not oscillate under some conditions?

It should be 100% a-stable as it can not stay in non-oscillating state.

Antti

Costs are no problem, it's a university project and not a design for production. I thought a crystal in combination with the cpld would need less power than a dedicated oscillator. Could you give me a hint where to find a

Thanks, Michael

Antti,

That is exactly what I meant (and also echoed by other posters).

When is a not gate not a not? When it has too much delay.

Austin

Antti Lukats wrote:

Of course, I'm looking for an oscillator for the transmitting cpld. He also needs 100 MHz to generate the data stream but as far as I know there is now DCM or PLL in a CoolRunner 2. Or am I wrong? On the receiver side power and oscillator is no problem.

Michael

Interesting target - why is the resistor such a problem ? There are bigger headaches in FPGA osc than the resistor..

-jg

Look at Maxim and Linear - they have a number of SOT23 Oscillators that are designed to give quite good precisions (for manchester), in

If you are brave, a LC osc can be built with a CPLD Inverter ( no resistor needed )

- tho at 100Mhz the Tpd is a size-able chunk of half-period. Start at 10-20Mhz, and lower L/C, to see if 100Mhz is practical.

You can also make a ring-oscillator, using just the PLD delay elements: this has the lowest precision, but manchester can auto-baud

for low power CPLD clocking notes, take a look at this

As often happens with benchmarks, the really usefull info is other-other. Here it is the Xilinx/Lattice relative infos - any Altera-others info will be carefully filtered :)

-jg

A more important question is WHICH frequency it oscillates at ! :) At lower slew rates (not this case), you can get multiple oscillation effects : At the thresholds, the extreme (excess) gain can give parasitic oscillations, or edge-fur, and that's NOT nice on a clock source !

-jg

Back in the 1970's, an engineer I was working for decided to save a part on a design and use a spare 7414 inverter rather than a 7404 inverter as an oscillator.

A TTL inverter, like the 7404, properly connected, makes a good oscillator. A 7414, which is a schmitt-trigger inverter, doesn't.

Yes, it would always oscillate. But only sometimes at the correct frequency. More often at the third or fifth harmonic of the crystal. And sometimes higher harmonics.

This left me with the idea that a good engineer should make sure that an oscillator design is a good design before building boards. Not afterward.

When I simply xor the NRZ data with the clock signal I get spikes which isn't surprising. So I create two 50 MHz clocks from the 100 MHz clock that are phase-shifted by 90 degree (by using rising and falling edge of the 100 MHz clock). Then I invert one of the two clocks depending of the NRZ data bit. Finally the two 50 MHz clocks (one of them modulated by the data to send) are xored and I have my manchester signal. Because now the outputs of two flipflops are xored there is nearly no time difference between them and the output is fine (my theory, don't laugh Peter ;) ). Of course the incomming clock must have a 50% duty cycle. I haven't tested it in silicon but a Post-Fit simulation with modelsim shows a very good signal and I hope this is a good sign.

Right, but in our application bandwidth is not a problem at the moment (optical link). We need to save power and so I try to use the smallest cpld possible.

Thanks also for the infos of oscillator manufacturers. I'll look tomorrow, it's time for bed now in germany.. ;)

Michael

Hi,

Thank you all for your help. I think everything is clear to me now.

Michael

gosh the 7404 and 7414 are totally different chips (in the context of making oscillators). it wasnt much of an engineer who tried crystal osc with 7414.

and CPLD osc about the same as from above should work. sure it has to tested to work properly on the correct freq and not harmonics

Antti

I'm sure you meant this, but I'll post it anyway. I'd rather say it has to be _designed_ to work properly. Trial and error is, as I've found through trial and error, a terribly inefficient way to do projects. Cheers, Syms.