I have a spartan 3 starter kit board.
I need to generate a clock of 1,5MHz.
It has an analog oscillator at 50Mhz.
What should I do?
I thought to multiply 50Mhz for 3 then divide for 100, but in what way I can realize that?
Now, as clock signal I have BUS2IP_CLK, from OPB BUS.
In what way I can connect to analog oscillator?
Many Thanks Marco
Ah, you have to try and work in powers of two! How accurate do you need the clock to be?? You could just divide by 32... Giving 1.5625 MHz. Ben
can realize that?
Mhhhh... there is a little trouble.
This clock must drive an LCD which has a timing fixed between: 1,535508 Mhz and
1,344537 MHz.Do you have other ideas?
realize that?
What will you do with this clock? Just drive an output or have internal logic clocked with it?
Göran
Well, because your required clock is so much slower than your oscillator...
Count the 50MHz clock, and every 'n' ticks toggle a T-Flip-Flop. f = 50MHz T = 20ns f = 1.5MHz T = 666.6ns T/2 = 333.3ns
counting 17 ticks of the 50Mhz takes 340ns, using this signal to toggle would give a 'clock' of frequency T/2 = 340ns, T = 680ns, f=1.47us
Bang in your spec. I don't know your exact application however so this may be a poor way of implementing for you.
Ben
Mhz and 1,344537 MHz.
Use the DCM to multiply your 50MHz to 150MHz and divide is a simple way. DCMs will also fractions but watch the input and output frequency limits.
There is a tool in the ISE toolset "Architecture Wizard" that can help you define the DCM with little pain and will tell you the limits for what you want to do.
John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.
can realize that?
I will try every methods.
Many Thanks to everyone!
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Mhz and 1,344537 MHz.
Hmm, sound not too demanding. Just divide the 50 Mhz by 33 and get 1,51 MHz. Thats it. If you need exact 50% duty cylce, divide by 34 (yielding in 1,47 MHZ)
Regards Falk
Just a quick (silly) question.. You have your clk signal coming in on a clk pin, you put it though a DCM or two and then it goes off to a global clk net in the FPGA.. Thats all fine with me..
In putting the clk though some logic (divider/counter) instead of DCM's, does the synthesis tool still put the end product on the global clock net?? I would hope that it does, but I'm worried that it would just treat it as another signal, due to the modifications that have been made...
Thanks
on
global
Xilinx will let you do crazy things to clocks before you put them on the global clock net, with no objections.
Marc
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