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There are 80975 individual articles here that are part of 14943 discussions
Please see below the list of the most recent and the best rated articles in Field-Programmable Gate Arrays

The most recent discussions

Cyclotomic FFTs

April 25, 2017, 12:07 am

I've been researching cyclotomic FFTs. There is a lot of literature (Fedor enko, Trifinov, Costa, etc.) about using this technique for calculating the syndrome and doing the Chien Search in Reed-... Read more »

glitching AND gate

  [ 2 ]
April 23, 2017, 1:34 pm

I have a question about how FPGAs handle signals into combinational logic. I have following setup: always @(posedge interrupt_check) interrupt_detect Read more »

how to convert analog signal cccam video to digital using systemc

April 12, 2017, 5:57 pm

Hi In the context of a university research, I try to convert the signal coming from an analog camera (1000tvl camera style) to obtain a digital signal and save it in a file in format h264; All using... Read more »

versatile_FFT core has no output

April 11, 2017, 5:53 am

I am trying to use , but after I run make all, data_out.txt and res.txt are all empty. Anyone have same experience ? Read more »

FPGA as heater

  [ 2 3 ]
April 11, 2017, 1:13 am

We have a ZYNQ whose predicted timing isn't meeting decent margins. And we don't want a lot of output pin timing variation in real life. We can measure the chip temperature with the XADC thing. So,... Read more »

How to download ISPLSI 1032 and how to program it?

April 7, 2017, 7:13 am

ISPVM 18.1 and ISP (HW-USBN-2A) are connecting and downloading and it says that there is no information of ISPLSI 1032 Chip continuously. I tested 10 boards and it is hard because I have the same pr... Read more »

handshacking between modules, best practices ?

April 4, 2017, 3:08 pm

Hi, Last weekend, I was continueing on my small project to use a FPGA as DAC. I now use a hardware DAC (tlc5615). So I have two modules, a top-level module for the DDS and an additional module ... Read more »

Simulation of PCIe at TLP level

March 24, 2017, 9:23 am

Hi, has anybody simulated PCIe at TLP level? I would like to feed a 1x PCIe endpoint interface with data as if it was inserted into a host PCIe slot. I need some pointers to documents or code descr... Read more »

Lattice Semiconductor XP2 Brevia 2 help on keyboard controller

March 15, 2017, 4:57 pm

I have an IBM Model-F capacitive keyboard. I would like to design my own keyboard controller for it. I understand logically how to do it, but I need help with the mechanics. Would somebody be in... Read more »

The Lord calls out to you for repentance, salvation

March 11, 2017, 1:33 pm

The message is simple: He wants to forgive your sin and give you eternal life in the paradise of God. If you have sin, you need a savior. And all of us have sin. And all of us need a savior. J... Read more »

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The best rated discussions


VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free ...

UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectur... Read more »


Lowest Power Design in an FPGA

What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that... Read more »


ICTP Open Hardware Initiative – Invitation to part icipate in an open-surve...

Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP - UN... Read more »


Software for FPGA-based PC scope

Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in... Read more »


lowest-cost FPGA and CPLD

I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give m... Read more »


Call for beta users for Sigasi integration with Altera Quartus

Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We hav... Read more »


Job - Promotion - 2D/3D Bildverarbeitug - FPGA

Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folge... Read more »