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There are 81667 individual articles here that are part of 15023 discussions
Please see below the list of the most recent and the best rated articles in Field-Programmable Gate Arrays

The most recent discussions

the FPGA one-shot

March 16, 2018, 6:18 pm

I finally got a test case for my FPGA async one-shot idea, hacked into a build for something else. I got 17 different one-shots, with various pin locations and speed/drive strength settings. htt... Read more »

How to handle a data packet while calculating CRC.

  [ 2 ]
March 12, 2018, 11:02 am

Hi, I'm trying to process a Ethernet type package. Suppose if i have detected S FD and now have a Read more »

Lattice or Microsemi?

March 7, 2018, 9:56 am

What are thoughts on these two vendors goods? I like that they have cheap(er) PCIe options. My intended use case is to learn about HW and HDL development with an existing strong OS development ... Read more »

Microsemi now Microchip

March 3, 2018, 9:28 am

In case anybody missed it: Hans Read more »

Is Zynq7000 leaky?

February 18, 2018, 12:35 pm

Does the Zynq7000 family contain any stored charge circuitry on the chip? The manual says there is On-chip boot ROM, but is it mask-programmed or flash? If there are flash cells, then what other S... Read more »

Most power efficient FPGA?

February 12, 2018, 11:51 pm

Hi, I have been away from in-depth FPGA development for maybe a decade! I am looking to design an embedded camera product where power use is key. I'd like to use an FPGA for some video manipulation ... Read more »

Scripts to maintain list of addresses in VHDL core communicating with SW vi...

February 11, 2018, 2:00 pm

Last time I had to prepare a firmware for FPGA, that contained a complex hierarchy of blocks and subbblocks, containing registers and arrays of registers on different levels of hierarchy. Those regis... Read more »

Clock distribution /Resynchronizing

January 23, 2018, 4:20 pm

Hi all, I would like to create and distribute a master clock and sync pulses to a n umber of boxes throughout a system. There will be some skew between the sig nals, of unknown sign. Probably the... Read more »

Go to church this Sunday

January 13, 2018, 9:28 pm

You see me write about sin and condemnation, and eternal Hellfire (damnation), and also how to avoid that end by coming to Jesus, and asking Him to forgive you and save you from Hell. But how do ... Read more »

My invention: Coding wave-pipelined circuits with buffering function in HDL...

  [ 2 3 ]
January 11, 2018, 1:56 am

Hi, A wive-pipelined circuit has the same logic as its pipeline counterpart exc ept that the wive-pipelined circuit has only one stage, a critical path fro m the input register passing through a p... Read more »

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The best rated discussions


VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free ...

UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectur... Read more »


Lowest Power Design in an FPGA

What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that... Read more »


ICTP Open Hardware Initiative – Invitation to part icipate in an open-surve...

Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP - UN... Read more »


Software for FPGA-based PC scope

Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in... Read more »


lowest-cost FPGA and CPLD

I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give m... Read more »


Call for beta users for Sigasi integration with Altera Quartus

Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We hav... Read more »


Job - Promotion - 2D/3D Bildverarbeitug - FPGA

Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folge... Read more »