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Please see below the list of the most recent and the best rated articles in Field-Programmable Gate Arrays

The most recent discussions

We are looking for invited speakers for our conferences and seminars: 5th R...

July 1, 2018, 4:46 pm

We are looking for invited speakers for our conferences and seminars. Our main interest will be talks about reconfigurable market (FPGA). But we are having problems getting their names and contac... Read more »

8 bits vs. 9 bits in RAM Blocks

June 29, 2018, 8:22 pm

The Xilinx, Altera/Intel and the mainline Lattice devices all support RAM blocks in widths of multiples of 9 bits. Some other devices only have RAM widths of multiples of 8 bits or less. Does this... Read more »

Stepper motor controller

June 6, 2018, 4:42 pm

Hello all, I used Hamsterwork's stepper motor controller , there position out for leds etc. How i can make give position back.. I.E. I want ... Read more »

How to analyes IBERT ip results for highspeed signals?

June 5, 2018, 8:49 am

Hi, I just started working with IBERT ip from xilinx. Can anyone suggest some references to look into to analyse the ip results and how to adjust the proper 2d eye scan? Thank-You in advance. Read more »

How to chnge this VHDL code into Verilog code

May 31, 2018, 11:38 am

architecture structural of prince_core is type round_constants is array(0 to 11) of std_logic_vector(63 downto 0); type intermediate_signals is array(0 to 11) of std_logic_vector(63 downto ... Read more »

SPL2019 - Call For Papers

May 28, 2018, 6:33 pm

========================= ========================= ========== CALL FOR PAPERS IEEE - X Southern Conference on Programmable Logic (SPL2019) April 10th to 12th, 2019 Borges Cultural Center, Bu... Read more »

Searching for info about very old FPGA devices

May 27, 2018, 4:38 pm

Hello. My name is Rodrigo and I am from Argentina. I was looking for very o ld datasheets without success :-( (I searched a lot in google,, alldatasheets, and more places...). I obtain... Read more »

Communication between HDL simulation and user software via ZMQ

May 27, 2018, 10:45 am

I develop systems were the FPGA-based hardware will use message-based commu nication (via Ethernet, USB or another communication channel) with remote s oftware. Those systems require thorough testi... Read more »

Re: Very low pin count FPGA

May 21, 2018, 5:46 pm

corporation/ICE40UL1K-SWG16ITR50/220-1960-1-ND/5129490 Xilinx has the XC95xxXL series of CPLDs, starting at 44 pins quad flat pack with leads. Very easy to hand solder. These have an internal ... Read more »

CAN Sniffer on Altera DE2-115 Board

May 15, 2018, 10:26 am

Hi there, I am trying to implement a CAN sniffer on an Altera DE2-115 evaluation boar d with the Terrasic AD/DA data conversion card (High Speed Mezzanine Card ( HSMC) via SMA. I am using two A/D ... Read more »

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The best rated discussions


VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free ...

UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectur... Read more »


Lowest Power Design in an FPGA

What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that... Read more »


ICTP Open Hardware Initiative – Invitation to part icipate in an open-surve...

Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP - UN... Read more »


Software for FPGA-based PC scope

Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in... Read more »


lowest-cost FPGA and CPLD

I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give m... Read more »


Call for beta users for Sigasi integration with Altera Quartus

Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We hav... Read more »


Job - Promotion - 2D/3D Bildverarbeitug - FPGA

Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folge... Read more »