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There are 82475 individual articles here that are part of 15091 discussions
Please see below the list of the most recent and the best rated articles in Field-Programmable Gate Arrays

The most recent discussions

Microchip UNI/O controller core for FPGA

June 13, 2019, 7:51 pm

Hi, I needed to access the Microchip 11AA02E48 EEPROM located on a FPGA board. Unfortunately, I couldn't find any VHDL/Verilog sources of a UNI/O controll er. Therefore, I have decided to writ... Read more »

bare-metal ZYNQ

  [ 2 ]
June 12, 2019, 11:32 pm

Assume I'm a pointy-haired boss trying to help one of my guys. I think that... The Xilinx ZYNQ (FPGA+ARM on a chip) has a hard boot loader. It figures out what the boot device is (serial flash, SD... Read more »

Nallatech BenBlue-II software

May 28, 2019, 7:02 pm

Hello folks, I try to use an old FPGA card from Nallatech, it is a BenNuey PCI card. I have the FUSE software, but I am missing the CD for the DIME card named BenBlue-II and Nallatech, unfortun... Read more »

Problem in ADV7611 with Interlace Input

April 24, 2019, 8:44 am

Hello folks, We are developing demo Aplication for HDMI input and output. for this we are using PicoZed 7030 board with FMC HDMI daughter card. the daughter card consist of Adv7611 as HDMI receiver... Read more »

FIFO timing, the right way

April 22, 2019, 6:42 am

Hi all, I am working on a block that needs to accumulate (at least) K data items and then consume them in a burst, while the next group of items might be flowing in. As the items are not consumed... Read more »

Up/Down Binary Counter with Dynamic Count-to Flag

April 21, 2019, 10:39 pm

hello, i need to solve this problem in verilog:Up/Down Binary Counter with Dynamic Count-to Flag this is start cod: module DW03_bictr_dcnto_inst( inst_data, inst_count_to, inst_up_dn, inst_... Read more »

FPGA board on ebay

April 15, 2019, 2:35 pm

If anyone is interested I just got round to putting up a nexys Video artix-7 board on ebay. This is a private not trade sale. Read more »


April 1, 2019, 11:12 am

Hi, I am trying to design a state machine for bitslip function but simulations dont seem to be correct. I cant figure out where the bug is. here is the code and test bench. module bitsliplogic( ... Read more »

Replaceme EPROM by CPLD/FPGA

  [ 2 ]
March 28, 2019, 12:28 pm

We have a product that includes a small parallel OTP memory. These devices get very hard to get and no easy alternative is available that fits in the very small available space. A PLCC32 EPROM will... Read more »

TCS34725 Basys3 VHDL

March 26, 2019, 2:39 pm

Hi I am trying to use TCS34725 to identify Green and Red Colors, it has I2C interface and i could not find any I2C interface about this and i am not capable to write a protocol code what should I do ... Read more »

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The best rated discussions


VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free ...

UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectur... Read more »


Lowest Power Design in an FPGA

What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that... Read more »


ICTP Open Hardware Initiative – Invitation to part icipate in an open-surve...

Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP - UN... Read more »


Software for FPGA-based PC scope

Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in... Read more »


lowest-cost FPGA and CPLD

I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give m... Read more »


Call for beta users for Sigasi integration with Altera Quartus

Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We hav... Read more »


Job - Promotion - 2D/3D Bildverarbeitug - FPGA

Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folge... Read more »