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Please see below the list of the most recent and the best rated articles in Field-Programmable Gate Arrays

The most recent discussions

Go to church this Sunday

January 13, 2018, 9:28 pm

You see me write about sin and condemnation, and eternal Hellfire (damnation), and also how to avoid that end by coming to Jesus, and asking Him to forgive you and save you from Hell. But how do ... Read more »

My invention: Coding wave-pipelined circuits with buffering function in HDL...

January 11, 2018, 1:56 am

Hi, A wive-pipelined circuit has the same logic as its pipeline counterpart exc ept that the wive-pipelined circuit has only one stage, a critical path fro m the input register passing through a p... Read more »

Now - not so new cheaper FPGAs

January 10, 2018, 6:32 pm

I have used the Lattice XP3 FPGAs in a design I've made a lot of money from. The parts have gone EOL but Arrow bought some 70,000+ and is still trying to get rid of them. Seems they over estim... Read more »

HDL simple survey - what do you actually use

January 10, 2018, 2:17 pm

I'm trying to decide on which to use for a project as the main default that may include a number of freelance people. can you say which of these you actually use (the most) and have the best ski... Read more »

The contents of the Book of your life

January 5, 2018, 6:53 pm

When you stand before God, the books will be opened. Every thing you've ever done will be there written down in the books perfectly. No distortion. No twist. No bent. Only an accurate and true ... Read more »

TinyFPGA Boards

January 3, 2018, 5:55 pm The web site does not work 100% as there are some broken links, but all the pages are there. They currently offer three boards, A1/A2 provide two sizes of the Lattice XO2, ... Read more »

Qs on HDL library code and pipelining

January 1, 2018, 2:11 pm

Hello everybody, and Happy New Year 2018! I am new to digital design, here are some basic questions: In particular for algorithm acceleration (e.g. arithmetic, cryptography, etc.), does it make se... Read more »

FPGA one-shot

  [ 2 ]
December 14, 2017, 3:43 am

I have an async signal, call it TRIG, inside a Zynq 7020. At the rising edge of TRIG, I want to make an async one-shot. It will leave the chip as RX and reset some outboard ecl logic. Anything from... Read more »

Part of our daily prayers

November 21, 2017, 3:23 am

My son and I say prayers together each night before he goes to bed. Part of our daily prayers is the Lord's Prayer. This is the way we say it each night: Our Father, who art in Heaven, hallow... Read more »

Request for each of you

November 20, 2017, 3:42 am

A request for each of you Original post :!topic/alt.os.development/nvGbmY74C-4 To my fellow Usenet groupies: I come before you today with a request for each of... Read more »

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The best rated discussions


VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free ...

UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectur... Read more »


Lowest Power Design in an FPGA

What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that... Read more »


ICTP Open Hardware Initiative – Invitation to part icipate in an open-surve...

Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP - UN... Read more »


Software for FPGA-based PC scope

Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in... Read more »


lowest-cost FPGA and CPLD

I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give m... Read more »


Call for beta users for Sigasi integration with Altera Quartus

Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We hav... Read more »


Job - Promotion - 2D/3D Bildverarbeitug - FPGA

Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folge... Read more »