Field-Programmable Gate Arrays - Main Page

Do you have a question? Post it now! No Registration Necessary

Field-Programmable Gate Arrays - FPGAs, PLDs and other programmable logic ICs are discussed here
Web, RSS and Social Media interface to comp.arch.fpga
There are 82015 individual articles here that are part of 15063 discussions
Please see below the list of the most recent and the best rated articles in Field-Programmable Gate Arrays

The most recent discussions

What is the name of the circuit structure that generates a state machine's ...

  [ 2 ]
December 13, 2018, 1:45 pm

Hi, What is the name of the circuit structure that generates a state machine's jumping signals? I remember I looked at the circuit structure and wrongly remembered the structure name as decision tr... Read more »

Help with Pmod VGA on Altera

December 7, 2018, 11:09 pm

I have a Cyclone V GX Starter kit board, with Quartus 13.1: I'd like some help on setting this up to get a Pmod VGA device... Read more »

Estimating ROM gate count in ASIC

December 6, 2018, 11:02 pm

I've searched for this but to no avail. I'd like a function f(D,W), where D=depth and W=width, which provides an estimate of the gate count of a lookup ROM implemented in ASIC gates. Yes, I kno... Read more »

How to make Altera-Modelsim free download version to work?

  [ 2 ]
December 5, 2018, 4:45 am

Hi, I downloaded 11.0_modelsim_ase_windows.exe from Release Notes For ModelSim Altera 10.1b ... Read more »

How to write an "alias" statement

December 4, 2018, 8:37 pm

Hi, I have a register array with each register having (pointer & data), now I hope to display each of two parts using 2 different names for easy reading in simulation. Here is code defining the reg... Read more »

Why choose a IOT smart digital lock?

December 4, 2018, 12:16 pm

Smart locks are sure to become every homeowner?s favorite. They off er the same level of security as typical mechanical door locks, but provide a range of alternatives to the mechanical key, and a... Read more »

Engineer for Xilinx Zinq in Barcelona

November 29, 2018, 10:27 am

Contact me!! At Read more »

Periodically delayed clock

  [ 2 3 4 ]
November 27, 2018, 4:42 pm

I'm preparing designs for a CPU that will be coded in Verilog on a Terasic Cyclone V GX starter kit dev board. I have a clock running at N MHz, and I have some logic that may take longer than the ... Read more »

Need Information about Implementing of Modbus protocol in fpga ( mostly spa...

November 26, 2018, 10:08 am

Hello folks, I wanted to implement Modbus protocol on fpga. I don't know how to start? I read various documents on internet but didn't got any clear idea. basically my aim is to make... Read more »

Simple system to manage register access in hierarchical Wishbone-connected ...

November 20, 2018, 8:55 am

Hi, I needed to provide convenient access to registers in an FPGA design intern ally interconnected with Wishbone/IPbus bus. There is a wonderful tool - wb gen2 in the OHWR directory, but it doesn... Read more »

Click here for other recent discussions »

The best rated discussions


VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free ...

UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectur... Read more »


Lowest Power Design in an FPGA

What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that... Read more »


ICTP Open Hardware Initiative – Invitation to part icipate in an open-surve...

Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP - UN... Read more »


Software for FPGA-based PC scope

Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in... Read more »


lowest-cost FPGA and CPLD

I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give m... Read more »


Call for beta users for Sigasi integration with Altera Quartus

Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We hav... Read more »


Job - Promotion - 2D/3D Bildverarbeitug - FPGA

Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folge... Read more »