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Please see below the list of the most recent and the best rated articles in Field-Programmable Gate Arrays

The most recent discussions

Student seeking for Internship in Digital Design

September 29, 2019, 5:44 pm

Respected members, I'm a 3rd-year undergrad, majoring on Electronics & Communication Engineering at IIEST Shibpur, India. I have been experimenting on my Artix-7 Basys-3 board since my 2nd-semest... Read more »

Here is new definition for keyword "if_2", version 2.

September 27, 2019, 3:42 am

Here is new definition for keyword if_2, version 2. It is developed based on many discussions after my first post: New keywor d if_2 is suggested for dealing with 2-write port memory. New keyword... Read more »

New keyword "if_2" for HDL is suggested for dealing with 2-write ...

September 25, 2019, 9:53 pm

Hi, In my opinion, using a 2-write port memory is a mature technique and its im plementation in any chip is never a secret. Hardware designers in HDL often use 2-write port memory in their applic... Read more »

How to write a correct code to do 2 writes to an array on same cycle?

September 24, 2019, 6:49 pm

Hi, Here is a code segment showing 2 methods doing 2 writes to an array with 2 different addresses on the same cycle: 1. p1: process(CLK) is begin if CLK'event and CLK = '1' then if C1 ... Read more »

[Fully Funded Scholarship] Research Assistantship (Spring, 2020) at the Gra...

September 23, 2019, 7:18 am

Research Assistantship (Spring, 2020) at the Graduate School, School of Sof tware, Hallym University, Korea The [Advanced AI-Communication Lab] and [AI Accelerator Design Lab] of the Hallym Unive... Read more »

PipelineC (again), dct example, looking for help/interest

September 7, 2019, 8:11 pm

Hi folks looking for feedback on PipelineC. Ideas of what to implement next . I will point you to a recent reddit post which ultimately points to GitHub. Read more »

Re: Philips LA PM3585 disassembler software wanted

August 28, 2019, 8:13 pm

Hi, I would be highly interested in the PM3585 disassembler software Regards smed Read more »

Bayer Pattern to RGB VHDL CODE

August 11, 2019, 7:38 am

Please VHDL Guru's i got 8 rows Bayer signal from MT9 parallel data camera , could someone help me or share VHDL code to convert from Bayer pattern to RGB ? Read more »

Why differences between Merly-type and Moore-type clock-gated state machine...

August 9, 2019, 8:53 pm

Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? I need help to understand a puzzle: Merly-type state machine generates outputs wh... Read more »

VHDL TIME support in Vivado

August 9, 2019, 5:49 pm

Y'all. It's 2019. TIME has been in VHDL since what, 1987? And yet Vivado remains unable to successfully divide an amount of time you want to wait by a clock period to get a compile-time intege... Read more »

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The best rated discussions


Microchip UNI/O controller core for FPGA

Hi, I needed to access the Microchip 11AA02E48 EEPROM located on a FPGA board. Unfortunately, I couldn't find any VHDL/Verilog sources of a UNI/O controll er. Therefore, I have decided to writ... Read more »


Lowest Power Design in an FPGA

What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that... Read more »


VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free ...

UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectur... Read more »


Software for FPGA-based PC scope

Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in... Read more »


lowest-cost FPGA and CPLD

I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give m... Read more »


ICTP Open Hardware Initiative – Invitation to part icipate in an open-surve...

Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP - UN... Read more »


Call for beta users for Sigasi integration with Altera Quartus

Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We hav... Read more »


Job - Promotion - 2D/3D Bildverarbeitug - FPGA

Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folge... Read more »