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There are 81230 individual articles here that are part of 14963 discussions
Please see below the list of the most recent and the best rated articles in Field-Programmable Gate Arrays

The most recent discussions

VHDL or Verilog?

June 21, 2017, 12:08 pm

I've been given conflicting device on which language to use. There are people I would consider to be expert professionals who tell me to use VHDL, and others who tell me Verilog. Most everybody t... Read more »

VHDL Verification components ? The obvious solutio n to efficient reuse

June 21, 2017, 7:05 am

How would you assure safe and efficient reuse of an FPGA design module for some stand-alone functionality? Let's consider this for a simple example like a UART. Now what would you do ? You coul... Read more »

Create FPGA to replace 1974 MOSTEK MK5017

June 20, 2017, 1:09 am

Hi Everyone, Perhaps you may have a skill to create FPGA and create a clone for 1974 MOS TEK MK5017, famous clock chip by Heathkit. They used this chip on model GC- 1005 and run with Panaplex disp... Read more »

Whups. Lattice Diamond says my package does not exist.

June 16, 2017, 4:40 am

Hi all. I'm stopped. Lattice Diamond does not offer a configuration for designing w ith my part in the 48-VFQFN package. The LCMXO2-640HC-6SG48I is not availab le in the drop-down configuration me... Read more »

Article about using Non-Project Mode

June 2, 2017, 10:55 pm

Hi! During the discussion about Test Driven Design? I promised to write a paper about Non-Project Mode and how it helps with testing. The problem is that I have never written any article. Moreover,... Read more »

baud_generator (16x baud) used in UART transmitter logic

June 1, 2017, 12:30 pm

For , how is the output of baud_generator (16x baud) used in transmitter logic ? I only see there is a transmitter timing control block in the ... Read more »

ZAP : An open source ARM processor (feedback)

May 28, 2017, 12:45 pm

Hi, I am the author of the Gihub project ZAP ( ). It is a 10-stage pipelined ARMv4T compatible soft processor core with cache and memory management support. I develop... Read more »

fpga zigbee interface

May 25, 2017, 5:16 am

i have spartan6 atlys(LX45) board, can anyone suggest me how to interface zigbee to this board to communicate with pc.thnx Read more »

Accelerating Face Detection on Zynq-7020 Using High Level Synthesis

May 23, 2017, 6:44 am

Hello, here is my question: Purpose: realize face detection on zynq-7020 SoC Platform: Zedboard with OV5640 camera Completed work: capturing video from camera, writing into DDR for storage and rea... Read more »

Spartan 6 Digital controlled oscillator

May 17, 2017, 8:42 pm

Hello, What is the best way to implement a 30 MHz clock generation circuit that can be dynamically controlled to provide fine frequency offsets in a Spartan 6, the clock is to be used in... Read more »

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The best rated discussions


VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free ...

UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectur... Read more »


Lowest Power Design in an FPGA

What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that... Read more »


ICTP Open Hardware Initiative – Invitation to part icipate in an open-surve...

Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP - UN... Read more »


Software for FPGA-based PC scope

Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in... Read more »


lowest-cost FPGA and CPLD

I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give m... Read more »


Call for beta users for Sigasi integration with Altera Quartus

Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We hav... Read more »


Job - Promotion - 2D/3D Bildverarbeitug - FPGA

Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folge... Read more »