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There are 82733 individual articles here that are part of 15130 discussions
Please see below the list of the most recent and the best rated articles in Field-Programmable Gate Arrays

The most recent discussions

No more gate-level simulation. for Cyclone V !!!


April 2, 2020, 11:50 am

Hello, I'm dealing with some fast state machines and gate-level-timing simulation of some components has been very helpful. Now using a Cyclone V I found that I can't do timing gate-level timing ... Read more »

Fight the coronavirus 100% and save LOTS of CASH -- Combattez le coronaviru...


March 28, 2020, 7:43 pm

Protect yourself and your loved ones ! KILL the coronavirus right now ! And save LOTS OF CASH New tested, scientificly proven and amazing antivirus against coronavirus using Chloroquine and Colchi... Read more »

PipelineC - C-like almost hardware description language - AWS F1 Example


March 22, 2020, 1:15 am

Hi folks, Here to talk about PipelineC. https://github.com/JulianKemmerer/PipelineC/wiki What is it?: - C-like almost hardware description language - A compiler that produces VHDL for specific d... Read more »

Using EDA tools at home


March 19, 2020, 11:13 am

Need to use your company EDA tools from home, here are some tips: 1) First of all, the most important solution is to speak to your EDA vendor ary license (if you are an existing customer). 2) If y... Read more »

How to generate bits info for a record structure?


February 13, 2020, 11:30 pm

Hi, I have a data record designed as follows: type DATA_RECORD_t record I1: unsigned(7 downto 0); I2: unsigned(15 downto 0); end record; I want to get its bit number and don't want to manu... Read more »

Code block in icestudio


February 13, 2020, 9:43 am

Hi, I'm trying to program a TinyFPGA BX to provide 3 registers to emulate an FDC9266, the bulk will later be done using an ATMega ucontroller. To sort out the A0,nCS,nRD,nWR,nDACK, I have inserted... Read more »

how to suppress assertion warnings in gtkwave?


February 7, 2020, 7:22 am

hello, is there any way to suppress assertion warnings from std.numeric in gtkwave simulator? thank you Read more »

Apple eBook on Educational CPU design using FPGA


January 14, 2020, 1:53 am

https://books.apple.com/us/book/implementing-a-cpu-using-fpga/id802454238 Read more »

Displays - Apple Mac vs. IBM PC


January 8, 2020, 4:00 am

I bet the Apple still have a huge leg up on PCs when it comes to displays. Yeah, they both have the same hardware these days, but the way the softwar e manages things is so much better on the Mac... Read more »

Optimizations, How Much and When?


January 4, 2020, 7:59 pm

My projects typically are implemented in small devices and so are often spa ce constrained. So I am in the habit of optimizing my code for implemented size. I've learned techniques that minimize... Read more »

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The best rated discussions

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5

Microchip UNI/O controller core for FPGA


Hi, I needed to access the Microchip 11AA02E48 EEPROM located on a FPGA board. Unfortunately, I couldn't find any VHDL/Verilog sources of a UNI/O controll er. Therefore, I have decided to writ... Read more »

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5

Lowest Power Design in an FPGA


What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that... Read more »

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5

VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free ...


UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectur... Read more »

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5

Software for FPGA-based PC scope


Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in... Read more »

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5

lowest-cost FPGA and CPLD


I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give m... Read more »

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5

ICTP Open Hardware Initiative – Invitation to part icipate in an open-surve...


Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP - UN... Read more »

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5

Call for beta users for Sigasi integration with Altera Quartus


Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We hav... Read more »

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4

Job - Promotion - 2D/3D Bildverarbeitug - FPGA


Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folge... Read more »