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There are 82286 individual articles here that are part of 15074 discussions
Please see below the list of the most recent and the best rated articles in Field-Programmable Gate Arrays

The most recent discussions

MachXO2 internal clock tolerance / accuracy

February 14, 2019, 4:32 am

Hi everyone! I have a hard time finding the tolerance / accuracy for the internal oscillator for the MachXO2. I seem to remember it being around 5%, which isn't really that great. Can anyone point ... Read more »

Testing (please ignore)

February 8, 2019, 4:11 pm

Please ignore Read more »

Is it possible to implement Ethernet on bare metal FPGA, Without Use of any...

  [ 2 3 ]
February 4, 2019, 6:29 am

Hello folks, Let's say I have Spartan 6 board only and i wanted to implement Ethernet communication.So how can it be done? I don't want to connect any Hard or Soft core processor. also I have loo... Read more »

Open Source Synthesis Tools

February 2, 2019, 3:30 am

I know there are some open source simulation tools for Verilog and/or VHDL... I can't recall which or if there are simulators for both languages. I believe there are significant shortcomings in any ... Read more »

Xilinx Artix-7 SoM with 8 x GTPs

January 30, 2019, 10:24 pm

Hello, I'm looking for a Xilinx Artix-7 SoM (or board..) with at-least 8 x GTP transceivers , preferably 16 , exposed to the connector. Any pointers will be much appreciated. Thanks ! Read more »

ARM + FPGA CPU Module running Yocto Linux?

  [ 2 ]
January 30, 2019, 5:13 pm

Is there any ARM + FPGA CPU Module running linux using any of: * NXP i.MX6/7/... * Texas Instrument Sitara AM335x or better * Microchip SAMA5 * Renesas RZ/xxx It needs to be connected to a low p... Read more »

Altera Cyclone replacement

  [ 2 ]
January 25, 2019, 2:58 pm

Hi, We got an old design with an Altera Cyclone FPGA (EP1C12F324). These are probably obsolete (Can't find any info on them on the Intel site, Farnell is out of stock, etc.). Currently active are ... Read more »

Need help to understand: Efficient Multi-Ported Memories for FPGAs

  [ 2 ]
January 14, 2019, 7:54 pm

Hi, I cannot understand the following paper: Efficient Multi-Ported Memories for FPGAs FPGA has a structure with 1 write port and ... Read more »

initializing a small array in Verilog

January 12, 2019, 10:34 pm

In my Verilog code I have this line: reg [1:0] ip_list [0:3] = { 2'd2, 2'd1, 2'd0, 2'd1 }; Both Icarus and Vivado seem happy with it and it does what I expect. However, I recently discovered Ve... Read more »

Can I use Verilog or SystemVerilog to write a state machine with clock gati...

  [ 2 3 4 ]
January 5, 2019, 4:29 am

Hi, Can I use Verilog or SystemVerilog to write a state machine with clock gating function? I know VHDL has no such function and want to know if Verilog or SystemVerilog has the clock gating functi... Read more »

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The best rated discussions


VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free ...

UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectur... Read more »


Lowest Power Design in an FPGA

What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that... Read more »


ICTP Open Hardware Initiative – Invitation to part icipate in an open-surve...

Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP - UN... Read more »


Software for FPGA-based PC scope

Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in... Read more »


lowest-cost FPGA and CPLD

I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give m... Read more »


Call for beta users for Sigasi integration with Altera Quartus

Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We hav... Read more »


Job - Promotion - 2D/3D Bildverarbeitug - FPGA

Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folge... Read more »