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Please see below the list of the most recent and the best rated articles in Field-Programmable Gate Arrays

The most recent discussions

New(ish) FPGA Company

November 5, 2018, 1:01 am

I hadn't heard of this company before. They seem to be making a number of FPGA devices. Unfortunately all the docs are in Chinese. Anyone know much about them? Google ca... Read more »

FPGA Market Entry Barriers

  [ 2 3 ]
October 18, 2018, 3:22 pm

I was wondering what the barriers are to new companies marketing FPGAs. So me of the technological barriers are obvious. Designing a novel device is not so easy as the terrain is widely explored... Read more »

Schematic FPGA Design on twitch

September 27, 2018, 11:55 pm

tomorrow from 20:15 cet until open end live on my channel schematic design on fpga. check it out Read more »

Need magic incantation to prevent synthesizer misoptimisation

September 23, 2018, 1:03 am

Hi all! I'm having a problem with the synthesis and P&R tools introducing a unnecessary gate in a critical path. Consider the following verilog: reg [31:0] mem_dataintomem = 32'd0; alwa... Read more »

Strange thing, my FPGA HDMI output cannot work with cheap chinese HDMI Exte...

September 22, 2018, 3:08 pm

I bought HDMI extender over optical fiber for $125, from Alibaba. HDMI Extender works well when Source is my laptop, but when source is my FPGA board,there is a problem. I enabled TMDS, HPD, DDC, ... Read more »

Need Help regarding I2C Protocol testbench

September 18, 2018, 11:04 am

Hello folks, I am trying to get a VHDL testbench running with the VHDL I2C core model. I am using spartan 6 fpga and using a simple state machine. The problem with simulation result is that it is ... Read more »

Need Advice regarding Interfacing of Max9850 audio DAC with spartan 6 FPG...

September 7, 2018, 10:11 am

Hello Folks, I am trying to interface MAX9850 Audio DAC with spartan 6 FPGA with I2C Interfacing. I'm Using VHDL Language For coding. Does Someone worked on this before? or worked related to this... Read more »

System Verilog Import package error

September 7, 2018, 8:51 am

Hello, I have a few packages that I have written like this: package A; -- -- endpackage package B; import A::* --- -- endpackage package C; import A::*; import B::*; endpackage In th... Read more »

What to do with an improved algorithm?

September 3, 2018, 10:17 am

Hi, I think I've got a really good way to improve a commonly used & well establ ished algorithm that is often used in FPGAs, and it all checks out. The imp lementation completes the same tasks in ... Read more »

Re: Cheaptest FPGA board for Computer Architecture

August 16, 2018, 8:24 am

On Wed, 15 Aug 2018 19:00:03 -0700 (PDT) [snip] The boards I have bought are shipped 5000km for free, and one at a time do not attract customs charges. The Icestorm tool chain is open source, s... Read more »

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The best rated discussions


VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free ...

UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectur... Read more »


Lowest Power Design in an FPGA

What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that... Read more »


ICTP Open Hardware Initiative – Invitation to part icipate in an open-surve...

Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP - UN... Read more »


Software for FPGA-based PC scope

Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in... Read more »


lowest-cost FPGA and CPLD

I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give m... Read more »


Call for beta users for Sigasi integration with Altera Quartus

Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We hav... Read more »


Job - Promotion - 2D/3D Bildverarbeitug - FPGA

Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folge... Read more »