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Please see below the list of the most recent and the best rated articles in Field-Programmable Gate Arrays

The most recent discussions

Re: Very low pin count FPGA

May 21, 2018, 5:46 pm

corporation/ICE40UL1K-SWG16ITR50/220-1960-1-ND/5129490 Xilinx has the XC95xxXL series of CPLDs, starting at 44 pins quad flat pack with leads. Very easy to hand solder. These have an internal ... Read more »

CAN Sniffer on Altera DE2-115 Board

May 15, 2018, 10:26 am

Hi there, I am trying to implement a CAN sniffer on an Altera DE2-115 evaluation boar d with the Terrasic AD/DA data conversion card (High Speed Mezzanine Card ( HSMC) via SMA. I am using two A/D ... Read more »

CPLD 1.8V to 3.3V bidirectional SDA

May 8, 2018, 2:59 pm

I have a small design flaw with a new sensor, ICM20948, into a PI device. I need to make the SDA bidirectional and level shift SCL, int, and fsync. Vo ltage level on the sensor board is 1.8V the P... Read more »

Sharing VHDL Verification IP

May 4, 2018, 7:22 am

Sharing VHDL Verification Components (VVC) within the FPGA/VHDL community h as previously been difficult because there was no standardised way of inter facing to and controlling these VVCs. A solut... Read more »

verilog reg usage

April 28, 2018, 1:47 am

Does Read more »

Xilinx Custom IP accessing 16-bit bram

April 27, 2018, 9:47 pm

Hello, I have used Xilinx core generator to synthesize a bram with width of 16 bit and depth of 80k, resulting a 17-bit address. Let's call them bram_data, and bram_addr. I am connecting the br... Read more »

Free Webinar Thursday: UVVM ? The standardized o pen source VHDL testbenc...

April 24, 2018, 11:40 am

The webinars are hosted by Aldec as follows: Thursday 26 April: EU: 3:00 PM ? 4:00 PM (CEST) : 12 US: 11:00 AM ? 12:00 PM (PDT): Read more »

engineered data path versus inferred data path

April 21, 2018, 1:30 pm

Seem to get better results when using inferred data paths? E.g. letting the synthesis tools insert the multiplexers where they see fit gives better Fmax than laying out the datapath in complete deta... Read more »

FPGA selection recommendation

  [ 2 ]
April 14, 2018, 3:06 pm

I need an FPGA chip with about 100 GPIO pins and capable of hosting a CPU with an existing Linux port, mainly to run a web server. I would like to connect it to a 16-bit DRAM, so there should exi... Read more »

Altera Cyclone V SoC availability...

March 31, 2018, 4:51 am

I can't find it anywhere. No one carries Cyclone V SX/T, only plain E or Gx... Read more »

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The best rated discussions


VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free ...

UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectur... Read more »


Lowest Power Design in an FPGA

What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that... Read more »


ICTP Open Hardware Initiative – Invitation to part icipate in an open-surve...

Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP - UN... Read more »


Software for FPGA-based PC scope

Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in... Read more »


lowest-cost FPGA and CPLD

I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give m... Read more »


Call for beta users for Sigasi integration with Altera Quartus

Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We hav... Read more »


Job - Promotion - 2D/3D Bildverarbeitug - FPGA

Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folge... Read more »