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Please see below the list of the most recent and the best rated articles in Field-Programmable Gate Arrays

The most recent discussions

Bayer Pattern to RGB VHDL CODE


August 11, 2019, 7:38 am

Please VHDL Guru's i got 8 rows Bayer signal from MT9 parallel data camera , could someone help me or share VHDL code to convert from Bayer pattern to RGB ? Read more »

Why differences between Merly-type and Moore-type clock-gated state machine...


August 9, 2019, 8:53 pm

Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? I need help to understand a puzzle: Merly-type state machine generates outputs wh... Read more »

VHDL TIME support in Vivado


August 9, 2019, 5:49 pm

Y'all. It's 2019. TIME has been in VHDL since what, 1987? And yet Vivado remains unable to successfully divide an amount of time you want to wait by a clock period to get a compile-time intege... Read more »

Lattice XO3D New


July 12, 2019, 4:03 pm

It looks like Lattice has announced a new FPGA product that suits my needs. I've always preferred non-BGA devices because they complicate the PCB fab rication with the need for fine pitch and ver... Read more »

New uses of FPGAs


July 8, 2019, 6:45 pm

FPGAs are used in a wide variety of applications from automotive to computing and space. Why are they not used inside optical modules? Read more »

How do big compagnies use Verilog/VHDL for processor designs?


July 2, 2019, 3:34 pm

I have a question on how big companies like Intel/AMD use VHDL and Verilog internally for their processors. For example, if they implement an ALU. Do they implement the ALU on an RTL-level or do th... Read more »

HOW TO READ A 64 BIT REGISTER IN 2 CLOCK CYCLES IN VERILOG


June 28, 2019, 8:35 pm

There is a 64bit input that is stored in register. A single clock cycle can read 32bits at a time. For implementing this 4x1 mux is used as 32bit imag e is divided into 8bit. The problem I'm facin... Read more »

Unique uses for the DSP48


June 28, 2019, 12:26 am

I've tried to figure out how to use the Xilinx DSP48s for Galois arithmetic t unary XOR, which can be used for GF(2) matrix multiplication, but the mul tipliers themselves aren't of much use for Ga... Read more »

Microchip UNI/O controller core for FPGA


June 13, 2019, 7:51 pm

Hi, I needed to access the Microchip 11AA02E48 EEPROM located on a FPGA board. Unfortunately, I couldn't find any VHDL/Verilog sources of a UNI/O controll er. Therefore, I have decided to writ... Read more »

bare-metal ZYNQ

  [ 2 ]
June 12, 2019, 11:32 pm

Assume I'm a pointy-haired boss trying to help one of my guys. I think that... The Xilinx ZYNQ (FPGA+ARM on a chip) has a hard boot loader. It figures out what the boot device is (serial flash, SD... Read more »

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The best rated discussions

rating
5

Microchip UNI/O controller core for FPGA


Hi, I needed to access the Microchip 11AA02E48 EEPROM located on a FPGA board. Unfortunately, I couldn't find any VHDL/Verilog sources of a UNI/O controll er. Therefore, I have decided to writ... Read more »

rating
5

Lowest Power Design in an FPGA


What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that... Read more »

rating
5

VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free ...


UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectur... Read more »

rating
5

Software for FPGA-based PC scope


Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in... Read more »

rating
5

lowest-cost FPGA and CPLD


I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give m... Read more »

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5

ICTP Open Hardware Initiative – Invitation to part icipate in an open-surve...


Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP - UN... Read more »

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5

Call for beta users for Sigasi integration with Altera Quartus


Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We hav... Read more »

rating
4

Job - Promotion - 2D/3D Bildverarbeitug - FPGA


Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folge... Read more »