Z80 instruction

Perhaps the idea is to detect when the value of OUTERCOUNT wraps around from 0xFFFF to 0? That is, 2**16 incrementations after OUTERCOUNT was last zeroed. Would that be a reasonable time-out period here? It is the longest period that can be counted with 16 bits.

--
Niklas Holsti
Tidorum Ltd
niklas holsti tidorum fi
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The code does just test for a timer roll over, BUT maybe the HL is being loaded with a value that is non zero to start with. That way it counts up from a set value. Testing for zero is very easy. Testing for a particular 16 bit number is a bit harder. You need to look at where OUTERCOUNT is getting initialized at.

Jim

I didn't list the interrupt but the code is: LD HL,0 LD (OUTERCOUNT),HL

And the initialsation is (for IAR assembler): OUTERCOUNT: defw 0

So it is definitely going to be set to zero. I guess it does just cound a roll over. The commentary elsewhere mentions a timeout of 8 seconds so this could well be it as 16,536 interations could feasibly take that long.

Thanks for your help folks.

This code increments OUTERCOUNT and jumps to ERROR if OUTERCOUNT was 0xffff before the increment.

If OUTERCOUNT is zeroed in an interrupt handler once per second and this code is not run more than 2^16 times per second ERROR will never be jumped to.

65,536

Just testing...

As Niklas pointed out, it is detecting 0xffff as the count limit. It also points out the slavish use of Z80 extensions to the 8080 code set, which is simpler, and in this case probably faster and more compact. Assuming this is a subroutine to be called as a watchdog check (ask if you need translation to z80 mnemnonics):

; Post increments (outercount), aborts when 0xffffh on entry. ; f, h, l disturbed check: lxi h,outercount inr m rnz; non-zero, wasn't ffh inx h; was ffh, carry, check high byte inr m rnz; non-zero, wasn't ffh ; " fall thru to error routine: error: whatever

Without disturbing the a register. 8 bytes of code versus 16.

--
 
 
 
 "A man who is right every time is not likely to do very much."
                           -- Francis Crick, co-discover of DNA
 "There is nothing more amazing than stupidity in action."
                                             -- Thomas Matthews

Further to the replacement code I gave earlier - that is subject to interrupt in the middle, and can then glitch. It should be called with:

di call check ei

and, if it diverts to error, error should do an ei.

--
 
 
 
 "A man who is right every time is not likely to do very much."
                           -- Francis Crick, co-discover of DNA
 "There is nothing more amazing than stupidity in action."
                                             -- Thomas Matthews

Thanks for that. I'm actually in the process of converting it all into C for the 80188. This watchdog isn't strictly necessary because I've got an external hardware watchdog too but it's better to be safe than sorry. The rest of the code I'm converting is so hideously bloated that 8 bytes here won't help me much but I do appreciate the sentiment. Thanks again.

FWIW, if the code gets interrupted *every* time somewhere between lines

1 and 3 above (unlikely, I know), then OUTERCOUNT will never be zeroed and the watchdog will trip!

I'm assuming HL is also preserved during the ISR?!?

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, 
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

I suppose that is possible but it is so unlikely that, if it did happen, I would suspect that there was trouble elsewhere. However, I disable interrupts before the increment and enable them afterwards so it should never happen. Of course the purpose of this is to detect problems with interrupts...

Yes it is. All the registers are preserved.