What is the preferred way of doing a context switch on the ARM?

I=92m asking, because I see no clean way to do it. On stack based machines you simply =93pushall=94 onto the active task=92s stack, switch stacks, and do a =93popall=94. The ARM makes this difficult because when it switches to a privileged mode, the active task=92s stack becomes =93invisible=94, and the CPSR gets saved into the SPSR (as opposed to being pushed onto the stack). Thanks!

Reply to
Michael
Loading thread data ...

Op Fri, 29 Aug 2008 07:45:34 +0200 schreef Michael :

User-defined task code is only run in User or System mode, which both use the 'unaliased' registers. On an exception, the processor starts using alternative registers, but you can go to System mode to access those unaliased registers and push them (and the SPSR as well, of course).

--
Gemaakt met Opera's revolutionaire e-mailprogramma:  
http://www.opera.com/mail/
Reply to
Boudewijn Dijkstra

h
n

=A0

=A0

om/mail/

Yes, but I was looking for a clean way to do it (no mode changing). Also there's the question of what register to use for the STM / LDM instructions. Evidently you need to push a register onto the privilege mode's stack. I would think that there would be a cleaner way...

Reply to
Michael

formatting link

The architecture is designed to use some privileged mode (e.g. supervisor) to do the context switch. Do not attempt to fight it.

--
Tauno Voipio
tauno voipio (at) iki fi
 Click to see the full signature
Reply to
Tauno Voipio

tch

hen

use =A0

ing =A0

=A0

a.com/mail/

Not fighting it at all, just don't see a clean way to do it in a few instructions. Do you have any ideas?

Reply to
Michael

This is the clean way, because it's the only right way. ;)

I believe it was designed this way to allow for short & fast ASM-only exception handlers. Only if you need more registers, then some PSR-switching is required.

That's why they have a stack, and that's what this stack is for. And if you intend to call a function from the IRQ exception (such as an interrupt process function), then you need to push R14 anyway.

But there isn't. Welcome to the dirty realm of possibilities! :)

--
Gemaakt met Opera's revolutionaire e-mailprogramma:  
http://www.opera.com/mail/
Reply to
Boudewijn Dijkstra

itch

when

o

=A0

s

=A0

f =A0

=A0

om/mail/- Hide quoted text -

Thanks for your help. I'm surprised that the ARM architects didn't provide for this (easy context switching).

Reply to
Michael

They did - its called a Cortex M3 ;o)

--
Regards,
Richard.
 Click to see the full signature
Reply to
FreeRTOS.org

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.