Hi,
I am a mature student will be doing some complex VHDL and Verilog design work for my course. As well as having to create and test the functionality of the design (in both languages) I want to document how the design is put together and it's complex hierarchy.
Is there anything out there that will allow me to represent my design in some sort of hierarchical functional blocks to use as a documentation tool? As I want to use both languages for the design something that ideally can accommodate VHDL and Verilog.
I am happy using my normal editing system for the code design so I don't want a 'block-to-code' type of system.
Thanks for your help.
James.