My thanks to those who responded with OTS solutions. Having investigated several products, it is clear I need to narrow the search. I'm looking for an OTS solution that will allow automatic regression testing of the system/device, but not necessarily debugging when a problem is found.
What would be needed is a means to simulate key/button presses, and to monitor and interpret information that would be shown on the LCD display to determine pass/fail of a step in the test or the entire test.
So far, I have seen JTAG/BDM/Nexus based products that would access a chip's On Chip Debugging System. Various solutions provide a trace capability, as well as being able to set triggers and stops. Would a trigger be capable of interjecting a hard button (i.e., ON/OFF) action? Are OTS solutions "smart" enough to stop on a trap, compare target memory to the anticipated output, and then restart the target processor?
I really apologize for all these questions, but I'm trying to understand AT to make some strategic decisions. A million TIA for any tips, ideas, suggestions, comments.
-- Manjo A ship in the harbor is safe, but that's not what ships are built for. --William Shedd