I'm about to design the hardware for a new variable speed drive controller. Since I'm largely targeting high power systems, I certainly don't need to squeeze the last buck out of the controller. I am looking for processing power (determinism is very important so I think I need to steer away from "lighting fast from cache, dog slow otherwise" processors) Easy design cycle is also very important
I am a bit out of date on CPU's DSP's etc that are currently widely used, so if anyone has a better idea I'd be grateful to hear it.
Here is my current basic idea :
Core components sitting on the fast asynchronous memory bus : TI TMS320VC33-150 FP DSP 1024K x 32 bit fast async. SRAM EP1C12 Altera Cyclone FPGA
The FPGA does Hardware peripherals (PWM, encoder interface, ADC/DAC interface) Interface to slower memories (FLASH, NVRAM etc)
Here are some specific questions :
- Does anybody have a better suggestion for the architecture ?
- Where can I source async. SRAM's that will meet better than 9ns access times, since this is what I need to run the DSP at 75MHz external bus cycle ?
You didn't indicate the type of motor drive you were looking at but I will assume 3 phase motor from a 6-switch bridge. When you say high power are we speaking in kW or MW ranges?.
There are some chips that deal with the complete full vector control of bridge based drives for three phase motors. These can be interfaced to some quite simple processors and provide adequate performance. If you prefer not to be locked into these chips then there are a whole host of processors out there that have the capability to perform well in such tasks.
If you are just in need of speed and/or torque control then a full vector controller could even be created in FPGA incorporating a processor core, some memory and the necessary interlocking logic (to prevent shorting the psu through two devices down a chain) for the drives and is readily achievable from freely available core IP.
Before I point you in any specific direction though, perhaps you would care to reveal some more requirements for these drives that would enable us to get a better taset of what you are specifically after in the outcome of the design.
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Can you not find a chip with enough on-chip resource for the CODE memory ?
Look at the Analog Devices BackFin DSPs, which have fast RAM, and even this device from ST, which might do the whole thing in one chip ? [DSP.ARM.RAM.FPGA.ADC.DAC...]
formatting link
Freescale also have Motor Controller focused devices.
I don't want to tie down too much in the controller - yes, mostly 3phase AC via six switches, but certainly also 6 and 12 pulse DC, SR, multi-level etc
This is the reason for the FPGA, so I can give (for example) Vd, Vq and Angle demands to the FPGA, and it can take Vdc feedback and generate switching patterns for whatever power bridge is connected.
I plan to steer away from dedicated motor control devices ('2812 would probably be the favourite here) since they are a bit too specific (and I can certainly improve on their peripherals in a decent FPGA)
What I'm looking for is a platform that gives me the flexibility to do high-end motor control (i.e. more than standard vector control or DTC), where I can move functions easily from software to the FPGA as appropriate.
I'll also end up with lots of "user side" needs (function block edited applications, PLC network connectivity, nice PC front etc etc)
I'm pretty certain about the FPGA side of things, my biggest doubt is the DSP choice.
I think I'll end up limited by the instruction-fetch speed. If I can get fast enough async. memories I can run this at 75MHz.
I wondered about the 67x DSP's from TI. However these are quite extensively cached and I am concerned about this 'cause control code tends to be "do this bit really fast, then do this other bit really fast" rather than "go round and round doing this over and over again until you've got an mp3 file". Don't really enough to comment intelligently.
I recently used a monstrous PowerPC ('7457) and never really got the performance I was expecting (because I always had to go to L3 cache for the code)
What else is out there for the CPU ?
I'm looking for :
- Lots of MIPS (and / or FLOPS) (Ideally around 100MIPS)
- Really lots of MIPS over quite a lot of code without cache already hot
- Good OCDS (I'm assuming the days of bond-out ICE's are behind us at these speeds)
- Floating point is a big plus, but not the "be all and end all"
I know I'll have to look carefully at all the candidates myself, but I hoped to pick up on other peoples' experience from this group.
I was pointing to devices that have significant on-chip memory, and that means you get faster operation, and lower EMC/RFI issues, which probably matters on a large VSD. The STW22000 mentioned has a 300MHz ARM _AND_ a 600MHz Dual MAC DSP and 16MBits of Memory, which I thought was high grunt ?
Please don't toppost. It means either extensive editing or losing the context.
I wonder if you should consider two processors. One has to be quite fast, and output the precised control timings. The other needs to stand back and take a view, but do more computation. It can prepare instructions for the i/o processor, and it probably will not matter if it skips one cycle every so often. At any rate you will concentrate the timing problems in the interprocessor communications.
This doesn't sound like a system where skimping on hardware is advantageous. The dual system will also allow for mutual backup and some fail safe, which I expect will be critical.
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Paul has pushed our RTXcore FPGA solution. According to our use and evaluation of the RTX CPU core, it still has the best interrupt response, latency and determinism. Using a 20 MIPS core, you can do useful work 200ns (4 clocks) after an interrupt arrives.
The RTXcore design was originally done for a client who had a very sophisticated timing generator that took advantage of the RTX's determinism. When Intersil obsoleted the commercial and industrial grades of the RTX2000 device, they found that it was cheaper to clone it than to change architectures.
By combining the core and any additional peripherals on one FPGA, the final cost will be lower. You can evaluate the system using a Xilinx S3 starter kit.
Stephen P.S. for more details please contact me off line.
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