using 8051ports

Hi,

Just wanted to know if there is any way to use port P0 and P2 while accessing external memory, or do you have to go in for 8255s?

I want to develop an application which has a really low number of components on the PCB.

Thanks.

Reply to
Aliasger
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In article , Aliasger writes

Use 8051's with on chip memory. "standard" 51 types have 64K code and varying amounts of XData. "extended" versions up to 192KB code (Philips MX etc).

Then there are some other versions that have all sorts of on chip memory.

/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ \/\/\/\/\ Chris Hills Staffs England /\/\/\/\/\ /\/\/ snipped-for-privacy@phaedsys.org

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Reply to
Chris Hills

Then you probably should stay away from external memory. Memory is a pretty straightforward thing to integrate onto the micro's silicon, since, roughly spoken, memory is the same thing for everyone. Peripherals connected to the port pints aren't.

--
Hans-Bernhard Broeker (broeker@physik.rwth-aachen.de)
Even if all the snow were burnt, ashes would remain.
Reply to
Hans-Bernhard Broeker

You can achieve a low component count by implementing some peripheral devices into a CPLD or FPGA.

Rene

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Ing.Buero R.Tschaggelar - http://www.ibrtses.com
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Reply to
Rene Tschaggelar

Or, look for a higher-integration 80C51 variant. ST have uPSD with LOTS of FLASH/EE/RAM, meaning most designs can fit into one device - and a PLD for any 'glue stuff'. Their ramping uPSD33xx family include In System Debug

Atmel have 64/68 pin AT89C51ED2 variants, which give more ports.

-jg

Reply to
Jim Granville

You can use the ports if you provide adequate decoding, latching (output), and gating (input). To minimize the number of parts, try putting everything on one chip. ;-) Look at the STMicroelectronics MicroPSD

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which provides an 8051-compatible processor, lots of memory, a little programmable logic, and I/O pins.

They also have combo chips without the processor that you connect to a standard 8051, which adds back the I/O lines, as well as provide flash and RAM.

Thad

Reply to
Thad Smith

Thanks for the response.

But I also wanted toknwo about the ports. Can they be used while accessing the external memory? I read somewhere that they can and somewhere else that they can't be used for dual purpose.

Waiting for the reply.

Ali

Reply to
Aliasger

In theory,yes, but in practice no: you'd have to know exactly when the port is being used for external data/ address. If it's more program memory you need use flash versions (up to 64k). If it's RAM you're sunk as regards ordinary 8x51s. There are various extended derivatives with more ports (Cygnal etc.) Or use something like MSP430s.

Paul Burke

Reply to
Paul Burke

You mean the very same ports that are used for the external memory ? Well as long as you can guaranteed that during a port access no external memory byte is changed plus that during a memory access the port hardware is not reacting either. I'd not do it as it becomes a source of programming errors especially when using a compiler.

Rene

Aliasger wrote:

Reply to
Rene Tschaggelar

"Aliasger"

If you mean at the same instant, then no : During memory Access P2 drives HIGH addr ( normally from DPH ), and P0 uses ALE to MUX LOW adr, (DPL,R0,R1) with DataIN/Out.

for dual purpose.

Outside of the MOVX (or MOVC) cycle, the ports follow the Port SFR registers. So, if you take care to make the upper (eg) 4 bits of both DPH, and P2 match, you can drive 12 bit RAM/EE memory, and have 4 static output pins.

P0 has even more going on, as it shares ADR and Data during a memory cycle, so that restricts what you could use it 'shared' for in practical apps. KBD scan could be an option, but that does place the kbd lines onto the databus, which is not a great combination :)

-jg

Reply to
Jim Granville

Not in any usable fashion. I seem to remember that alternate data can be made available on one or two of the 12 clock cycles in the old 8051's but that is probably no longer true given that most modern 8051's use 6, 4, 2 or 1 clock/instruction.

Reply to
Albert Lee Mitchell

Yes... ports 0 and 2 can be used as address/data bus and as port IO in some very special cases. This is on HOOKs parts when used with ICE.

Hooks is a form of debug technology used with In-Circuit-Emulators. The ports and adress/data bus are multiplexed out on the same pins. However you need port reconstruction circuits on the outside (you will need to do your own ACIS/FPGA for this) and all the information on HOOKS to do it. This will cost you a LOT of money time *if* they will let you do it.

"They" being Metalink who invented the system and license it. It is used by many 51 silicon vendors, Atmel, Infineon, Philips etc and all the mid to high end 8051 ICE vendors.

The method can't be used in "normal" operation as is being implied by the O/P.

There is a description of HOOKs in the paper on embedded Debuggers at

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Regards Chris

/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ \/\/\/\/\ Chris Hills Staffs England /\/\/\/\/\ /\/\/ snipped-for-privacy@phaedsys.org

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Reply to
Chris Hills

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