USB 3.0 and 2.0 pins to different places

I was reading the datasheet for a USB switch chip recently:

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This chip supports both USB 3.0 (with its twisted pair unidirectional signals TX+/- and RX+/-) and USB 2.0 (with bidirectional D+/-). This particular example is a 2-to-1 chip: one device, two hosts, or two devices, one host.

What puzzled me is it has a mode where the Superspeed TX/RX pins and High Speed D pins can go to a different place. Eg for a single device, Superspeed pins go to host A and High Speed pins to host B.

Does this make any sense? Is there an application you might use to route that? I can imagine a niche where you only want to connect the High Speed pins (because firmware or whatever is broken for 3.0), but they don't have an 'off' mode, only an A/B select.

Is SuperSpeed alone likely to work? And how is a device likely to fare if there are two different hosts talking to its SS and HS pins?

It sounds like a bit of a strange feature, and I'm wondering why they included it.

Theo

Reply to
Theo Markettos
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I believe Superspeed alone does not work. I seem to recall initial communications is always over the high speed link, then the superspeed link can be established, no?

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Rick
Reply to
rickman

Thanks, that's what I thought: start on Low Speed and gradually ramp up the speed (and the power).

However, I noticed another example. This USB 3.0 hub chip:

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has 'Shared Link' mode, which is a fancy way of saying you can get more ports by sending the SS pins to one device and the HS pins to another. "for embedded applications" it says. But won't you have to do a fair bit of butchery to both the host and device stacks to make them start in SS? In which case it doesn't look much like USB any more. I thought a major feature of embedded USB was that either host or device is a commodity part, where you don't change the software stack?

Or are 'spec violating SS-only devices' a product out there?

Theo

Reply to
Theo Markettos

I'm not sure of an advantage to a device that starts in SuperSpeed mode. The connectors all have the full set of pins. Is saving two pins on a chip an advantage? What would be the goal?

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Rick
Reply to
rickman

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