I have a multi-drop two-wires RS485 bus. One node is the master and all the others are slaves. The master is the only node that is authorized to initiate a transmission, addressing one slave. The addressed slave usually answers to the master.
The bus is half-duplex, so every node disables the driver. Only THE node that transmits data on the bus enables the driver and disables it as soon as it can, just after the last byte. An interrupt (transmit complete) usually triggers when the last byte is totally shifted out, so the driver can be disabled immediately.
Of course, other interrupts can be triggered. What happens when interrupt X (whatever) triggers just before the "transmit complete" interrupt? The result is the ISR X is called, postponing the execution of "transmit complete" ISR. The RS485 driver will be disabled with a certain amount of delay. In the worst case, the driver could be disabled with a delay that is the sum of the duration of all ISRs that could trigger. [In this scenario, I think of ISRs that can't be interrupted by a higher priority interrupt.]
If a node on the bus is very fast and starts transmitting (the master) or answering (one slave) immediately after receving the last byte, but when the previous transmitting node is executing other ISRs, the final result is a corrupted transmission.
What is the solution? I think the only solution is to define, at the design time, a minimum interval between the receiving of the last byte from one node and the transmission of the first byte. This interval could be in the range of 100 microseconds and should be calibrated on the sum of duration of *all* ISRs of *all* nodes on the bus. It isn't a simple calculation.
Moreover, implementing a short "software" delay in the range of some microseconds isn't a simple task. An empty loop on a decreasing volatile variable is a solution, but the final delay isn't simple to calculate at the design time, and it could depend on the compiler, compiler settings, clock frequency and so on. Use an hw timer only for this pause?
How do you solve this problem?
[I know there are some microcontrollers that automatically (at the hw-level) toggle an output pin when the last byte is totally shifted out, but I'm not using one of the them and they aren't so common.]