Hi all.
I'm having some difficulty, and the Internet is really, really stingy with the answers. I need expert opinion.
I want to interface a FPGA to a DDR2 chip at 166 MHz. If I put the two chips side-by-side, do I *need* to length match the traces?
I've calculated that the biggest difference in trace lengths in my design is less than 1.8 cm (less than about 0.7 inches). If I put the two chips next to each other - say 1 cm clearance - the longest connection is going to be maybe 3 cm. Now, that's a lot of difference, relatively speaking, but 166 MHz is reeeally, really slow. The difference in arrival/departure time caused by the absolute length difference works out to about 60 ps. This is really supposed to be only about 2-3% of pulse length for data lines. Will this *actually* matter to the chips?
For reference, I'll length match the differential clock. Fortunately, all the pins align just right.
A lot of this uncertainty was sowed into my head by AN2582 from Freescale Semiconductor.