Totally off-topic, Cray-1 Hardware Reference Manual

Thanks for the pointer to this Interesting article.

Maybe someone someday will implement it with a few FPGAs :-).

Having worked with minis at that era, it is amazing that CRAY-1 had

2-8 MiB of fast (138 ns) bipolar static memory, when a mini of that time had up to a MiB of slow (1000 ns) core of dynamic RAM or 64-1024 words of bipolar cache memory.

I think it was a question of paying a king's ransom for an amazing turn of speed. In big-iron data processing it wasn't until dynamic CMOS RAM came along in the early '80s that really generous amounts of memory were available at a price businesses could afford. In 1978 we put the third megabyte of core onto a GCOS system and exposed a memory allocation bug. Apparently nobody had tried that before. Five years later system memory sizes had increased by an order of magnitude and transaction volumes (not I/O bound any more) by up to two orders of magnitude. That was when systems started to resemble these desktop things we have now.

Mel.

It was interesting to see that the manual described serial 3 and later of the Cray-1. The remains of serial 3 sit in the hall as an exhibit from my office at the NCAR Mesa Lab in Boulder. I actually had the opportunity to use it (mostly in a support role) between 1987 to 1989 when it was decomissioned after being used pretty much continuously since it was installed in 1977. I had a parallelized Mandelbrot image program that was written in C running under the batch Cray OS (COS). It is always amusing to tell someone their current laptop or cell phone has more computational resources, memory and storage than that large chassis they see in front of them.

-- Roberto Waltman

[ Please reply to the group, return address is invalid ]