TMS470R1A256 - Wiggler ARM-JTAG question

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Hi,

I'm using an ARM-JTAG dongle interface (which uses parallel port, and
is Macraigor Wiggler compatible) to program a TMS470R1A256 on a
TMS470-P256 board (made by Olimex). I have been able to load the
application to RAM and to flash, but when executed from flash, the
applicaton runs 16 times slowlier. Using the debugging feature of the
ARM-JTAG, I have stopped the execution in both cases, and compared
several registers (the ones listed below), and all of them have
identical values (both in RAM and flash execution).

GCR    0x00000008
PCR    0x00000001
SYSECR    0x00004007
CLKCNTL    0x00000010
MFBAHR2    0x00000020
MFBALR2    0x00000050
SMCR1    0x00000072
MFBAHR4    0x00000040
MFBALR4    0x00000010
WCR0    0x00000003
MFBAHR0    0x00000000
MFBALR0    0x00000190

I keep input "PLLDIS" always high.

Until I get a scope to delve into this, I was thinking that maybe some
of you already know why this is happening.

Thank you,

Re: TMS470R1A256 - Wiggler ARM-JTAG question

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I know nothing about this chip, but is the flash the same bus width as
the RAM? Zero wait state in both cases?


Re: TMS470R1A256 - Wiggler ARM-JTAG question

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From the datasheet:

"The A256 memory includes general-purpose SRAM supporting single-cycle
read/write accesses in byte, half-word, and word modes. The flash
memory on this device is a nonvolatile, electrically erasable and
programmable memory implemented with a 32-bit-wide data bus interface.
In pipeline mode, the flash operates with a system clock frequency of
up to 48 MHz. In normal mode, the flash operates with a system clock
frequency of up to 24 MHz."

"In pipeline mode, two words are read in parallel from the flash core.
Storing these two words in pipeline data buffers increases the
bandwidth of the data coming out of the flash core, which provides
effectively zero wait states on as many accesses as possible. In
pipeline mode, the flash data is always latched into the pipeline
buffer first, then read from the pipeline buffer to the CPU. Pipeline
mode removes the flash memory access time from the critical timing
path, which allows the clock frequency to be higher."


So it looks like in both cases the data bus is 32-bit wide. Regarding
speed, the tests I run were at SYSCLK12% MHz, and I don't think the
wait states can cause a difference of 16x. It looks like some of the
prescalers is not doing what it should be doing, according to the
value I read from the control registers.

Thanks a lot.

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