Hello everyone, I have a (maybe) simple problem I don't know exactly how to face up.
I am given a digital schematic design (which is made by a third person) that realizes simple bus peripherals inside a Altera MAX CPLD.
The design is quite simple: the address bus along with the data bus and the READ signals are brought as inputs of the CPLD (outputs are not considered here).
There is a combinatorial network which, starting from the adresses and the READ signal of the bus, derives some internal Chip Select signals used to drive the Clock of FFD registries.
Now, I am asked to perform timing analysis to such design to verify if it is feasible (I have the timing specs of the bus).
How can I perform such kind of *asynchronous* analysis? I am used to analyze pure synchronous circuits, but this situation is totally different!
Theoretically, I should verify that the propagation delay of the combinatorial decoding network is compatible with the timings of the FFDs, but actually I do not know exactly the timings of the FFD (I suppose they are not a fixed value but depend on the decisions of the place and route)
Paradoxically, I would be able to verify timings if the FFDs were realized as physical chips OFF the CPLD (verifying that the pin-to-pin combinatorial delay is feasible according to the external FFD chips timings).
How should I model such constrains when everything is modeled inside a CPLD? I am currently using Quartus II tools.
Thank you in advance, Primiano Tucci
-- Primiano Tucci
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