System Generator, Virtex 2 Pro and place & route simulations

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Before I write further, I'm not very proficient dealing with FPGA systems.
Recently I'm trying to implement a device using system generator targetted
at Virtex 2 devices. I've managed to simulate successfully to the map stage,
but I always get undefined output during my place and route stage testbench
simulation. (I've done my constraint files too). Thinking that some settings
are wrong, I target it at Virtex devices and it worked.

I wonder if any of you have any experience dealing with System Generator and
Virtex 2 pro devices? It has been quite a fustrating experience.

Thanks all!

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