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Re: super fast divide-by-N
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Interesting - is that DIV 2 in the IO area, or in the DCM itself - in
which case, are there pin restrictions to drive at 1GHz ?

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What jitter spec, would the DCM give ?
assume sub 100MHz out, and 1GHz sub ps jitter IP .

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-jg



Re: super fast divide-by-N
Jim,

Answers in the thread below,

Austin

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In the DCM.  Turns out the IOB is pretty good at receiving signals:  V2
stops at 1.15 GHz typically.  This is not well characterized, and you
are pretty much on your own here.

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For simple divide by 10, the jitter will be entirely from the tap
changes, which is ~50 ps tap in VII.  Since +/- one tap is the
theoretical best one can do, and in practice, you may decide the change
the tap incorrectly, that makes three taps the minimum possible, and
also the maximum if there is no other jitter.  That is 150 ps P-P period
jitter out of any output of the DCM, best case.

As a percentage of the period, 150 ps is not so bad at 100 MHz (10 ns,
or 10,000 ps).  That is 150/10,000 of a unit interval jitter, or 1.5% UI
jitter.

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Re: super fast divide-by-N

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  Look at OnSemi, under high performance counters, you'll find ones that
go 1.4GHz. You will pay for this performance :)
  If a few hundred Mhz is OK, then look at any modern 32 macrocell CPLD
[ Xilinx / Lattice ], and they are closer to $1
-jg


Re: super fast divide-by-N

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There are DDS's that can run off of a 1 GHz clock. The Analog Devices
AD 9858, I think it is. That might be massive overkill for what you are
doing.

Instead, you could divide the 1 GHz down by 4 or 8 using some kind of
prescaler, and then feed the resulting 250 MHz clock to a CPLD or
something which could implement whatever kind of divide-downs you want,
and produce multiple copies.

You don't say anything about jitter.

I dropped comp.dsp, because it seemed to have more to do with hardware
design.

--Mac


Re: super fast divide-by-N
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MC100EP016A :
3.3V ECL 8bit synchroneous Binary up counter,
operating frequency > 1.30GHz, LQFP32, 19.50$@1

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Re: super fast divide-by-N

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While a divide-by-N could be implemented with an up-counter and using
some gating to detect N and asynchronously reset the counter, this
will usually have some timing glitches. Usually a divide-by-N is
implemeted with a presettable down counter, when "0000" is detected, N
is loaded into the counter.

If you do not need the divide by 1, some synchronous presetting could
be used, i.e. the gating detects the "0001" state and let the next
clock pulse do the actual presetting.

This could be done with up-counters, but now the gating would have to
detect the N-1 condition to perform a synchronous reset at the next
clock pulse.

Paul
 

Re: super fast divide-by-N

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How about using the carry as synchroneous load ?

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

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