super fast divide-by-N

Lasse,

Nice to hear from you again! I think the OP might want a coherent division. Maybe not.

Jerry

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Reply to
Jerry Avins
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[.dsp removed. .fpga added]

These RfXOs are interesting devices, sub ps jitter, and 600-1.25GHz clock out. Not cheap, but they do change the clock conventions. Normally, you'd use a 80MHz xtal, and an RF synthesiser to create the GHz region clock.

CPLDs can clock to some hundreds of MHz now, but none released can get to > 600MHz.

Perhaps there will be enough demand for this type of GHz LVDS clock-in, that we will see FPGA, or even CPLD, with IP cells designed to divide this ?

On present process, it is quite doable; you could not clock the FPGA fabric at 0.6-1.25GHz, but you could divide from that, and get a phase locked, low jitter FPGA clock(s) - if the IOcells were designed to support it ?

-jg

Reply to
Jim Granville

I have been told that Virtex ( II to 4) the DCMs can divide down from a GHz, if you use the divide-by-two prescle option in the DCM. That means the DCM really runs on 500 MHz, which it is specified to do. Division ( even combined multiply/divide) with numbers up to 32 is no problem. You can multiply 500 MHz by 7 and divide by 27 (if those are your numbers). The virtual 3.5 GHz are not really being generated, it's all mathematical trickery. :-) For finer granularity, you can use DDS phase accumulators which, however, generate som jitter (+ or - half a clock period). Peter Alfke, Xilinx Applications

Reply to
Peter Alfke

... snip ...

And you will find that syncing that with the 1 GHz clock is more accurate than a countdown. There may be some 1 clock 1/2 period jitter because there will be some sort of error in 80Mhz oscillator wrt the 1 Ghz rate. The overall rate will be as accurate as the 80 Mhz oscillator. It also means you only need 1 D flip-flop that can clock at 1 Ghz.

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Reply to
CBFalconer

Interesting - is that DIV 2 in the IO area, or in the DCM itself - in which case, are there pin restrictions to drive at 1GHz ?

What jitter spec, would the DCM give ? assume sub 100MHz out, and 1GHz sub ps jitter IP .

-jg

Reply to
Jim Granville

If all you need is a divide-by (as opposed to an adder), a look-ahead scheme should make any "by" as fast as a flop and a few gates-n-wires. Pipeline the carries, if need be. If a pre-scaler is needed a Johnson counter is a good choice.

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  Keith
Reply to
keith

Jim,

Answers in the thread below,

Austin

In the DCM. Turns out the IOB is pretty good at receiving signals: V2 stops at 1.15 GHz typically. This is not well characterized, and you are pretty much on your own here.

For simple divide by 10, the jitter will be entirely from the tap changes, which is ~50 ps tap in VII. Since +/- one tap is the theoretical best one can do, and in practice, you may decide the change the tap incorrectly, that makes three taps the minimum possible, and also the maximum if there is no other jitter. That is 150 ps P-P period jitter out of any output of the DCM, best case.

As a percentage of the period, 150 ps is not so bad at 100 MHz (10 ns, or 10,000 ps). That is 150/10,000 of a unit interval jitter, or 1.5% UI jitter.

Reply to
Austin Lesea

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