STM32 PWM output accuracy issue.

Hello,

I've got an STM32F103Z part and I'm trying to generate a PWM output between

10Hz and 20Hz from the timer 1 peripheral.

Depending on how I set the timer 1 prescale value (timer 1 is on the 72Mhz high-speed bus), I get more or less accurate output results which can vary by up to 1Hz from the target frequency.

The only thing I can think of is that the external oscillator (8Mhz) is off, but I find this hard to believe since these are typically very accurate over temperature.

Any help on this would be much appreciated!

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microe
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An off-by-one error in setting one of the registers?

I can play with this on a dev board later today or over the weekend. To check my understanding of the problem, it is that the base PWM period should be set to a pre-determined value between 50 and 100 msec but when you aim for, say 15 Hz (66.667 msec), the actual base period is somewhere between 71.4 msec (14 Hz) and 62.5 msec (16 Hz), sometimes on the high side and sometimes on the low. Correct?

Are there also temperature extremes involved, or is this observed at room temperature with only self-heating occurring?

--
Rich Webb     Norfolk, VA
Reply to
Rich Webb

between

72Mhz

vary

Rich,

Thanks for the reply.

You are correct, I am comparing my expected vs. measured period for a given target frequency.

Testing for this has been done at a regulated room temperature (70 deg F).

I've tried two prescale values:

1) 72 (1 million high-speed clock counts per Timer 1 clock tick). 2) 720 (100K high-speed clock counts per Timer 1 clock tick).

Using a prescale value of 72 results in noticably less accuracy over the

10-20Hz range than using the 720 prescale value.

I've also used other prescale counts with varying degrees of accuracy. I see no trend towards better accuracy as I increase or decrease the Timer 1 prescale value.

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Reply to
microe

Errors of 1Hz are errors of 5-10%

So this is not making much sense. Check your measurements & setups for noise.

The classic uC timer reloads, and if you have 1MHz that should be a value from 100,000 to 50,000 for 10-20Hz, and your Frequency step size should be

1/50001u =3D 19.999600007999840003Hz

The 720 prescale will be 10x worse, 10,000..5000 and first Freq below

20Hz is now 1/(5001*10u) =3D 19.996000Hz At the 10Hz end, you are better off, first step above 10.000Hz is 1/((10000-1)*10u) =3D 10.001000100010001Hz
Reply to
Jim Granville

e

Hi Jim, a guy in a local (Bulgarian) forum complained that the ADC of some STM family (likely the same) began doing erroneous conversions from time to time (rarely) when he switches on peripherals above a certain number. That is, if he keeps some of them off the error does not occur. Sounded like a ground bounce or whatever logic error on chip to me. May be this is the same issue. The guy here also said the new version of the chip had some external cap pins which the old version did not have, could be if they really had the issue they are throwing capacitors at it in the new version (he did not know if it worked, had not tested the new ones).

But I have never used nor seen nor read any data about this chip, nor have I controlled the measurements, so this may well be totally wrong. Just communicating some (not mine) experience which might turn out to be relevant - or just wrong, however.

Dimiter

------------------------------------------------------ Dimiter Popoff Transgalactic Instruments

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Reply to
dp

72 shouldn't work at all (or at least, not as intended) since the auto-reload register (TIM1->ARR) is only 16 bits wide and you'd need to count to 100,000 for a 100 msec period with that prescale value.

I set up the dev board with a prescale of 720 (for 100,000 ticks per second) and set the ARR and CCR to 10,000 and 1,000 respectively to aim for a 10 Hz PWM frequency and a 10% duty cycle. The results were pretty rock solid, even with the JTAG running. It hit right on 10 msec pulses with a 100 msec period; no cycle-to-cycle variation.

Is it possible that you have UART1 also initialized? The STM32 chips do not allow two initialized peripherals to be connected to the same GPIO. They're a little less flexible in that regard as compared to some other processors that have registers to select "this" peripheral or "that" peripheral rather than just "the" peripheral.

Here's how I got there:

// Setup Timer1 for a PWM with a 10 Hz base period. // Aim the output at TIM1_CH1 on PA8. // We'll need to skip the setup of UART1, since they share pins, so...

#define USING_TIMER1

RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; // give timer 1 a clock

RCC->APB2ENR |= RCC_APB2ENR_IOPAEN; // give port A a clock GPIOA->CRH &= ~GPIO_CRH_MODE8; GPIOA->CRH |= GPIO_CRH_MODE8_1; // use low speed output mode GPIOA->CRH &= ~GPIO_CRH_CNF8; GPIOA->CRH |= GPIO_CRH_CNF8_1; // alternate function, push-pull

TIM1->PSC = 720; // 1e5 cps so 10 Hz is 10,000 counts TIM1->ARR = 10000; // start at 10 Hz TIM1->CCR1 = 1000; // and a 10% duty cycle TIM1->CCMR1 &= ~TIM_CCMR1_OC1M; // setup for PWM mode 1 TIM1->CCMR1 |= (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1); TIM1->CCMR1 |= TIM_CCMR1_OC1PE; // preload enable TIM1->CR1 |= TIM_CR1_ARPE; // auto reload preload enabled TIM1->CCER |= TIM_CCER_CC1E; // channel 1 output enabled TIM1->BDTR |= TIM_BDTR_MOE; // timer 1 main output enable TIM1->EGR |= TIM_EGR_UG; // update registers TIM1->CR1 |= TIM_CR1_CEN; // and enable the counter

--
Rich Webb     Norfolk, VA
Reply to
Rich Webb

That makes no sense whatsoever. If there's a difference at all, the higher timer base frequency timer should improve your accuracy, not impede it. So something must be fundamentally wrong with how you're doing this.

I think we've reached a point here where there's no point in going on with the discussion if you don't show more details of what you're actually doing. As Linus T. is so fond of putting it: talk is cheap --- let's see source code.

Reply to
Hans-Bernhard Bröker

given

F).

the

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microe

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