Splitting bidirectional pins?

You could you another spare pin to control a CD4066 multiplex thingummy,

martin

The pin is one of the 8 data I/O pins on a SRAM. Are you saying to take one of the other I/O pins for the 4066? Could I take a bit clock from my processor and use that instead?

-- Chuck

Duh, confussed, audio bit clock or what, from a cookery newsgroup:

If you want to narrow down the cause, please:

Post the formula you are using. (I know you told us the book and the recipe name, but we don't all have that book. So please copy the ingredient list.)

Tell us what method you are using.

Tell us whether you are using cups and spoons or weights to measure ingredients.

Tell us what brand (company and product name) of flour or flours you are using.

Tell us whether you are using a thermometer to check water temperature and dough temperature and, if so, what water temperature you are using and what dough temperature you are achieving.

Tell us how you are managing the stand mixer (are you timing it? what brand and model is it? what speed setting are you using?)

Are you timing the fermentation (first rise) or judging it by touch?

Are you timing the final rise (proof) or judging it by touch?

Is your kitchen air conditioned?

The more questions you answer, the easier it will be to diagnose the problem.

And the "size" thing.......

martin

Martin -- I completely understand.

OK..here goes. (I am a novice here..so please be kind.)

I have an ADC that is converting an analog audio signal at 32kHz and 16 bits per sample.

I am trying to delay the audio by up to 10 seconds (user selectable) by sending that serial bit stream through SRAMs to simulate a long shift register (or fifo.) Since I will need lots of memory (around 4 Mb) and there's no such thing as a 4Mb x 1 SRAM, I am forced to use expensive

1M x 1 or 256K x 1 chips, which have dedicated input and output lines. Since most everything else wider than 1 bit (except flash or FRAM, which are too slow or too expensive) have 8/16, etc. bidirectional I/O lines, I would like to see if I can use fewer and/or less expensive memory chips to do the delay. However, I am stumped by the bidirectional nature of the I/O lines on the wide SRAMs.

After I achieve my selected delay, the serial bits are sent back into the DAC and turned back into audio.

My address lines are generated by a series of 4040 counters and, hopfully, everything is synchronized through the clock in the Codec. (I'll be using a XTAL of 12.288 MHz.) I am trying to avoid the use of a microcontroller, if possible.

Hopefully, these ingredients are helpful....

A LOT better than the first question.

Making a FIFO using 4040 is pushing things....

If you want variable delays, you need TWO address sources WRITE address, and READ address. For a FIFO, you need two timeslots per codec timeslot: one that writes the present codec value, and one that reads the older (some-distance-back) already stored value.

ie you use bidirectional lines, one way at a time. Write/read/Write/read/Write/read/Write/read/ etc

if you REALLY want to use logic chips, look at the HC590 to replace the 4040 : that is a Tristate 8 bit Binary counter/latch (chain them up), you need one chain for READ_Address, and another chain for WRITE_Address, but you still need to interleave R/W, Select OE's on the 590's, and also somehow? delay the read counter start, to get the delay. Plus if it is all serial, you also need HC595/HC597 devices..

I'd look at CPLDs, or cheap ISP uC's with lots of pins, and an inbuilt SRAM interface, like the Atmel AT89S51 (sub $2, 1 off): use it like a logic device, to do the address and variable delays ....

-jg

I don't understand your problem. You're sampling at 32kHz which means you need to write to SRAM every 31us. That leaves *plenty* of time to interleave a read whilst your DAC is acquiring the next sample.

What's the mystery regarding bidir I/O lines? The direction of the SRAM lines is controlled via the OE/WE control inputs to the SRAM. You simply need to mux the output of your two address counters in sync with logic that enables the output of your ADC and the OE/WE lines.

i.e. when your ADC has completed another sample... enable the output of your "write" address counter enable the output of the ADC data bus/shift register enable the WE line on the SRAM (all taking care to honour setup/hold times for the SRAM) disable above then enable the output of your "read" address counter enable the OE line on the SRAM latch the data into your DAC (again, honouring the setup/hold times for your SRAM,DAC) disable above repeat forever

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, 
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

And yes, as Jim suggested, it's probably *both* easier and cheaper to use a uC with SRAM i/f...

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, 
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Thanks very much for your suggestions.

I will give a microcontroller a try. I have played around with an ATtiny2313 on an STK200, but it seems that something like an ATmega32 would support this project better. Hopefully, that, and some 'easy' assembly code would do the trick since my knowledge of software is pretty minimal...

Appreciate your help,

Charles

You could use an SRAM chip more effectively by chaining the bits: feed the data into D0, read it out from D0 and feed it into D1, then D2 etc. Use an 8 bit latch to store the byte you read from the SRAM and to write it back again. Connect Q0 to D1, Q1 to D2 etc. And try to use a CPLD instead of discrete counters, so you can make it a two chip (SRAM and CPLD) solution.

Meindert

"Meindert Sprang" schreef in bericht news: snipped-for-privacy@corp.supernews.com...

8

Or use two shift registers to convert 8 bit samples into 1 byte sample (and v.v. of course).

Antoon

An ATmega32 does not have an exteran bus interface. Use something like an ATmega8515 which does have an external SRAM interface. The address range is only 64K, but the easiest would be to map your SRAM into blocks of 32K. (From 8000H upwards in the AVR SRAM address range) If software is a problem for you, then using a small CPLD to control things may be easier.

Regards Anton Erasmus