SPI slave select signals

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View
Hi all,

In an SPI interface  i have got 4 slaves and one master
What i wanted to know is wether the master can assert two slave
selects(SS_N) simultaneously OR is there a restriction that master can
assert only one slave select.

Does SPI standard dictate anything!!!

Any comments on this would be appreciated.


Re: SPI slave select signals
Quoted text here. Click to load it

The slave will drive its MISO pin while selected.

Re: SPI slave select signals
Quoted text here. Click to load it

Depends on the design of the master.  The NIOS II used in the Altera
FPGA permits me to asers any number of the SPI select lines.

But also as has been pointed out if the slaves all try to respond with
data you've got problems on the SOMI singal line.


Re: SPI slave select signals
snipped-for-privacy@gmail.com wrote in news:1117455841.370215.303660

Quoted text here. Click to load it

The SPI can certainly assert multiple slave selects. The restriction is on
the slaves. No more than one slave can drive the MISO line at the same

There are many SPI slave devices that are write only (No MISO connection).


1. Configuring multiple data converters with the same instructions. You
might reset the parts with the same instruction and address the parts
independently for gain settings.


Al Clark
Danville Signal Processing, Inc.
We've slightly trimmed the long signature. Click to see the full one.

Site Timeline