Simple & small MCU with 4 UARTS

Sorry about the self reply, but I've just found that AVR have the

The "simplest" chip to use is not a simple chip really but amazingly simple to get it to perform these tasks. However I did answer this on another thread which I have included below.

From CAE thread "Does anyone know of a 4 port serial MCU?" Links:

or

Try the P8X32A Propeller. It's available in QFP44 or DIP40! and it has zero serial ports in hardware. But with eight 32-bit cores or cogs there are a quite a number of serial port objects in the public object exchange that can implement up to 4 smart "UARTS" per core. I say smart because each cog can handle the protocol and buffering etc. I frequently run multiple high-speed "UARTS" plus I demo'd a no-glue one-chip solution today running a mouse and playing space invaders on the TV complete with music and sound effects while it was handling multiple serial communications ports and protocols without any kind of latencies or glitches. I have done AVR, ARM, Renesas etc and I haven't looked back since this chip.

The chip is available for around $11 in one off quantities.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

eliben schrieb:

I haven't had any problems with them yet.

Very nice. When you say 'running a mouse' do you mean talking to a mouse with its own microcontroller or acting as the microcontroller running the mouse hardware input tasks?

JFox

A 16c554 also provides 4 ports, is in a 48pin pkg, and is available for less than $8, one off at digikey. And much better discounts in medium qty than the propeller. FIFOs on each port and no separate toolchain required to get the functionality, either. Works on 2.5V,

Jon

How is core-2-core communication?, complicated?, cpu intensive? trivial?

I'm just talking about a standard 5 button PS/2 mouse with CLK and DAT. The PS/2 keyboard and mouse object runs on one of the cogs and updates buffers and variables in common HUB RAM. Application software running on another cog just looks at those variables and the whole I/O thing operates completely transparently to the application.

The mouse START object is called with the port numbers for the CLK and DAT as such:- mouse.start(27, 26)

In the application a reference to the mouse might look like this:- 'Players Ship gr.clear8x8(mousex,mousey) gr.clear8x8(mousex+8,mousey)

also

if mouse.button(1) repeat i from 0 to numbad - 1 if bady[i]

Actually there is no "core-2-core" communications. Each core or cog is absolutely identical and they share the same I/O pins as well but they are all connected to a HUB-like RAM with a simple "rotary commutator" or "Propeller" scheme which guarantees equal access.

So then there is this core-to-hub communication using reads and writes between the COG and common HUB RAM. It's a bit like having an 8-port RAM with 8 independent CPUs connected to it and with each CPU having 32 I/O ports all "wired OR" together to 32 I/O pins.

Simple and surprisingly very effective. Note that there is a Prop II being designed that runs a lot faster, has more memory, I/O etc and may have other enhancements as well. But for now I know I can use this simple little Prop to do complicated tasks simply and cheaply.

Hi ,

I have used ATMEGA 2560 for one of our products ( 4 way UART switch/ Pipe). We operate it at 8 Mhz and can do 38400 easily on all ports. We didnt have any problems so far. More over the software tools are free i.e. WinAVR gcc + AvrStudio ( with winavr gcc as a plug in). ISP programmer(=A320) and USB JTAG Debugger(=A3200) are cheap as well comparatively.

Also there are open source libraries on the net that can get you started in a giffy!.

e.g.

Hope this helps. Happy new year.

Rate

rd/A...

Yes, it does! Thanks for letting me know about the chip.

Eli

With 32 I/O pins it sounds like it could easily use a cog to manage a mouse wheel and buttons directly inside the mouse instead of the 6805 or whatever is in there and have it update buffers and variables in the common HUB RAM just like the one currently doing the standard mouse interface protocol.

Was that a spin programming language example? It looks pretty simple.

Best Wishes

What do you think is the upper baud limit for 1 to 4 software bit banging UART on a fast AVR before a hardware UART is needed?

What are the upper limits using the hardware UART on a fast AVR?

Best Wishes

That's very much a "it depends" question. It depends on things like whether the UARTs are duplex (sending is much easier than receiving), whether they are all active at the same time, whether they are synchronized, how accurate the baud rates are known, what the noise environment is like (that affects the need for oversampling), whether you need to write it all in C or if you can use assembly (this is one of the cases where hand-crafted assembly can be *much* faster), and what else the processor is doing.

I wrote a 38.4 kbaud software UART on an AVR at 7.37 MHz with 4 times oversampling. That meant a timer running at 153.6 kHz, with 48 processor clocks between ticks. That's not a lot of time, but easily enough for the software UART written in assembly.

he

I appreciate that you don't want to learn a new micro, but for what it is worth, the PSoC CY8C29xxx series can be configured with 4 UARTs. The PSoC comes with configurable digital and analog blocks that can be set up in a multitude of ways within the constraints of the resources.

Also possible with the PSoC or with external gating on another processor is to have one UART communicating over multiplexed pins provided only one channel is operating at any given time.

-Aubrey

That mainly depends on the interrupt latency. With no other interrupts, the transmit part is no problem up to hundreds of kbps. Receive part is more difficult. For one software UART, the interrupt by the start bit can be used, which allows the speed of hundreds kbps also. For many uarts, the sampling of at least two times per bit is required. That sets the upper limit at about 100kbps.

The max. speed of the AVR hardware UART is CLK/8, i.e. 2.5Mbaud at

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

Bow many bytes is this shared RAM? Can one processor generate an interrupt on another one (without using up one of the common I/O pins)? How much ram and program memory does each core have? Wait, I found it here:

Is each core the "standard" Von Neumann architecture (program and data inabit different areas of the same address space), or is it Harvard (program and data are on separate busses and thus can be accessed simultaneously for greater speed, like DSP's, the AVR and several other microcontrollers)?

What's the programming language? Is there an assembler? What's the architecture of each core (or "cog") look like (number of registers, how they can be used in different instructions and addressing modes, approximate average cycles per instruction, etc.)? Is there a C compiler for it? Might there be a GCC port for it? (others might want to ask about C++, but for me it's a little hard to imagine using C++ for a microcontroller). I did read some blurb on the Parallax site by the designer, that it is what it is, that he hand-designed the thing rather than using the usual hardware-design tools and HDL's, and there won't be a bunch of slightly different verssions with different peripherals and such. Here it is:

The above page says this thing runs up to 80MHz, that's not too shabby, depending on what you're comparing it to. How much faster is "a lot?" ;)