SI and EMI training

The course was by Lee Ritchey called "High-Speed PCB, System Design, and Use of Simulation Tools" at UC Berkeley and it was three days, not the two listed at

While searching for the name of the class I found this link for an article on him and his training. It does not appear recent.

He is teaching a related course at UC Berkeley in Oct, "Signal Integrity and Its Effect on EMI and High Speed PCB Design". I expect it will cover a lot of the same material since the description is the same. It may even be the exact same class.

I figured someone like you would come along. You are pretty funny!

Paul Carpenter wrote:

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So many things :)

First, I do not apply rules of thumb blindly - I use a systematic approach to EMC/EMI and indeed all parts of my design. So covering a few things:

1. I try to follow the device manufacturer's exhortations on decoupling, although in my experience they specify far more than is truly necessary (as no doubt your instructor mentioned), but as I am not privy to the internal layout of the device, putting fewer devices on for decoupling is a risk I must weigh. There are many times I have indeed put fewer decouplers on a board than the chip mfr specified. I have the PeteS[tm] decoupling analysis tool (it actually is a spreadsheet) that I use.

1. Signal integrity consists primarily of maintaining the signal and preventing it from radiating. In the case of differential signals, this includes preventing differential mode to common mode conversions. As Howard W. Johnson says 'perfectly matched lines don't radiate'. Incidentally, I have a copy of his book 'High speed digital design. A handbook of black magic' on my shelf.

To answer a question: Internal common mode conversions on CML type drivers occurs for a number of reasons, but one of them is because the transistors are not a perfect match, there is *some* transient current during switching from one state to the other. Better decoupling reduces this effect. I use the term internal here to mean internal to a chip, not due to track mismatch (impedance or length). In this case, it converts to a common mode signal *on the power supply rail* which is why extra decoupling helps.

1. I am sure the course you did has great value, and indeed I am glad to see people doing such courses; at least you are now aware of the fact that thre is more to SI and EMC than simple decoupling. I am also certain your instructor is highly knowledgeable in the subject. He, of all people, would proably accept that 'nobody knows it all' and that some techniques practised by the unwashed masses may indeed have value.

1. Even on high density boards, I can always find room for a few extra decouplers (although maybe not what the mfr wants - see above). I have done boards with an average density of >150 pins/sq. inch and still managed to get a few extra caps on there - it also passed EMC testing by design (although I admit to thinking myself lucky) and had a 14dB margin at that.

2. When designing a system, you have to accept that you *manage* EMI because you can not eliminate it.

As I now have to fix dinner, I'll have to stop for now. More later perhaps :)

Cheers

PeteS

I would love to see your spread sheet if you are willing to share.

The class actually showed how to calculate the requirement for power plane decoupling based on the noise margin of the logic family. The chip manufacturer may not provide electrical info on the package, but you can always measure it. This is done by determining how many signals will change state in the same direction at the same time. For example a CPU or DSP may change the entire data bus and address bus at the same time. So you write a program that will do that. You then set a "quiet" pin to either a one or a zero and measure the resulting disturbance on the "quiet" output. This will give you a good measurement of the ground or power bounce from the parasitics. This number must be figured into your noise margin. After you have subtracted out the figures for ground bounce, crosstalk and possibly some items that I don't recall off the top of my head, you have margin left to allow some for power noise. After taking supply noise into account this can be used with the calculation of how much current is required to drive the transmission lines to figure the impedance of the power planes.

Of course this is way overkill for a simple MCU design. But if you have a number of high speed bus signals and lots of power being drawn from the supply, it will pay to do the calculations rather than the guesstimates that most engineers do.

Did HJ provide any test data to support his theory? A lot of things can happen according to theory, but the question is how significant are they?

I will be happy to learn from anyone who has something to offer. But so far the only discussion has been that there is more to SI and EMI than "theory". I don't doubt that, but no one has given me anything to work with. That's ok. I am not looking for free training. I just don't see anything else that is needed so far.

Of course you can always squeeze in another 0603 part on a board. But it is never free. Even if it does not add to the recurring cost directly, you had to take the time to find the room and guesstimate where to put it. The last board design I did we spent at least an hour or two working on placement due to trying to squeeze in the decoupling caps in a difficult design. Had I known then what I know now that the placement of the caps is not critical, I could have saved that time and done useful work. It is also likely that this board might have been done in 8 layers instead of 10 layers. It was not a big deal on this project because the government is paying the bill and we are only building 100 units. BTW, that is not my statement, that is everyone else on the program. Personally, I try to save the money, but I often get overrulled because others don't want to deviate from tradition.

Of course. But the management can be done before you put a unit in for testing rather than after. That is the only point. These things are science, not art, and can be understood and designed right the first time.

BTW, it is nice having a rational discussion of this without getting emotional. I appreciate the conversation. Please don't interpret anything I say as pushing your buttons as that is never my goal. I am just trying to respond to your posts and discuss the technical issues. Thanks for your informed opinions.

As it is a spreadsheet tailored for me, it's not necessarily perfect for everyone. I'll send it to your gmail address Tuesday or Wednesday with appropriate instructions for use. The basic postulate is that the decoupling should provide a total effective impedance of 1/10 of the effective impedance of a known impulse. Let's say we know there will be a Delta I of 1A at V = 1.2V. The effective dynamic impedance of the system is therefore 1.2 ohm for this simplistic example. The decoupling should provide a dynamic impedance (at the frequencies of interest) of < 0.12 ohm. The spreadsheet is set up for that sort of calculation and specifies maximum effective ESR vs. F for the decouplers as well as the capacitance required. There's also a section for ferrites for the required impedance at some F for the same sort of thing.

I usually use worst case for decoupling (and a lot of other things such as power supply impulse requirements). A lot of the things you note above is automatically done for me with my spreadsheet (that as I noted, I will send you), but I did it from hard experience - note that does not deny the theory; merely that a lot of it did not really exist when I started making it.

I agree completely. One can save a lot of space and heartache this way.

It is a physical property of transmission lines and much theory exists to support it. A perfectly differential signal (i.e. referred to it's complement) on a perfect transmission line will not radiate nor suffer loss. On a real circuit board, there will be loss (dielectric and skin effect losses dominate) and mismatch in both impedance and track lengths. When track lengths vary on a differential pair, the effective received differential signal has a loss proportional to the length mismatch. This is basic transmission line theory.

The loss of differential signal shows up as a common mode signal (it has to go somewhere) that may now radiate.

Consider a transmission pair of drivers that are complementary outputs (the definition of differential drivers) that simply switch current from one driver to another to change states (the definition of CML drivers). The transistors can never be perfectly matched and therefore switch on and off at very slightly different times. We have now defined a conversion from differential mode to common mode.

This is an extensive subject that I have actually taught classes on (in another life long ago :)

Perhaps if I were to say that much of the theory does not even exist you might see some of the problem. We still use a great deal of empirical data in this area simply because the theory is not yet properly fleshed out. Until we have more in the way of confirmed theory we will have to rely on experience and empirical results. I am active in a smaller community devoted to forming formal theories on this issue

- I'll talk at more length in email.

0603? I use 0402, 0201 and on occasion even 01005 parts :)

Tradition is something that has positives and negatives. Personally I try to balance the accumulated knowledge against my current issue. In highspeed EMC/EMI there really does not exist an accumulated wisdom. (Let's define highspeed as >500Mb/s for this issue).

I also try and save money, but I must also try and save time - it's annoying to have to say 'I did this and it worked but I am not certain why', but on the other hand it meant I got the product out quickly, imperfect as it may be. Sometimes one must get something out there even if it's not perfect.

As I noted, much of this is not yet fully characterised, and is therefore not 'recognised science'. Science it is, but until we fully characterise it much black art will remain. One major area that remains to be dealt with is systems level analysis tools. I can determine what might radiate, but until I can characterise the entire box, I won't know how the entore box may radiate it. I might be able to do it by hand, but there are a lot of variables involved :)

I never interpreted your statements as pushing buttons; indeed I am answering because I view it that way :)

Rational discussion is my preference too - I tend to lose interest in threads when they degenerate into slagging matches.

Cheers

PeteS

FWIW, although I haven't contributed, I'm enjoying, and indeed learning from, the discussion. More power to you all.

Steve

I'm glad. That is why I posted about this. I think that although there are clearly "gurus" who have done a good job of studying and learning the field, there are many more like myself who were picking up bits and pieces from various sources and did not really have a good understanding of the principles. This is not even mentioning all the misinformation that floats around out there. I wanted to open a discussion to see what others thought and to chalenge some of these misconceptions. I think the biggest misconception is the idea that SI and EMI are just too complex to analyze adequately beforehand and must be dealt with after a design is done as voodoo or black magic.

So its good that you have learned a bit from it.

I am curious, why did you pick 10%? Why would you need to use ferrites in power supply design?

What theory did not exist?

Interesting. It would seem to me that the signal lines themselves would not radiate significantly since they are closely coupled to a ground. So the noise you are referring to would be in the power circuit. Here the low impedance of the power plane would prevent this from appearing on any other signals. That was the point that Ritchey made in regards to EMI. If you don't have an antenna or you don't have noise, you won't have EMI. If the differential signals are properly designed to be very close to the power plane they won't radiate. If the power planes are designed to have very low impedance at the frequency of the impulse, they won't have noise.

Do you have any test data to show this is really an issue? Ritchey showed that the matching of differential pairs was not so critical when it came to SI, limited by the slew rate. This seemed to be very clear since the pair is not a coupled pair, but just two signals each of which are coupled to the power plane. I don't recall him specifically discussing EMI in this case, but I think my analysis above is correct. The noise would be a high speed triangle as one edge slews before the other starts. Then that edge stops as the second continues to slew.

____

---/ \---- Diff + ____ ___ \----/ Diff -

---/\---\/--- Noise

I'm not sure how well this will show, but perhaps you can see what I am thinking. The frequency of this noise is very high and related to the slew rate. This should already be coupled out of the design by the plane impedance.

Putting myself in Ritchey's place in the class, I think he would say that E&M theory is very complete and is all that is needed to deal with any of these problems. Perhaps I am assuming too much, but I got a pretty good feel for how he dealt with questions and objections during the course. He just kept going back to the basics and never would allow anyone to make things overly complex. I am still very impressed with his consistency of style and his level of success.

Yes, that is another thing that he suggested, that going smaller than

0603 is not a significant improvement. The 0402 is half the size, but two vias are required and once you add in the courtyard, etc, the difference is size is a much smaller percentage. Ritchey and I clearly share one thing, worsening eye sight and the small advantage of the smaller parts is not worth the trouble.

His method of power decoupling also makes it clear that using the physically smaller caps does not make a significant difference in the impedance of the power planes either. If needed you can just use a few more of the larger caps to make up the difference in your impedance calculations. But the key is to do the calculations which a lot of people seem to think is not worth the effort (not necessarily you).

I have nothing against doing whatever it takes to make something work. But that is what you do after you failed to make it work by analysis. What is the value of trying to produce a product and having it fail because the design took a shortcut? If you are not certain why something worked in the past, would you do it again on another design where it had to be right the first time?

If you have time to fool around with it after you have designed it, why don't you have time to do it right the first time?

What is not characterized? Ritchey frequently measured things himself either by designing a test board or using an eval board. His designs go up to at least 5 GHz and I think he said he is working on a 10 GHz design or has already done one. He does not leave one thing to chance, he uses calculations and simulations for every part of his design. If he does not have the data, he measures it!

No, but I think others here may view my discussion as trolling. I just want to put it on the record that this is not the case. If this turns hostile at any point, I will stop discussing it.

Exactly. Partly for me this is dress rehersal for discussing this with others at work. I can assure you that people there will not be willing to accept discussion and will consider much of this as heresy.

Thanks again!

10% is a good starting point. If I make the effective impedance of the decoupling system 1/10 of the dynamic impedance of the part we're decoupling, then the current path is dominated by the decouplers, not the power supply, which is some (inductive) distance away.

Ferrites are as basic in constant current systems as caps are for constant voltage. CML drivers (like their genetic predecessor, ECL) operate by switching current from one path to another. This helps minimise noise and is _very_ fast. We use ferrites on the I/O supplies to CML drivers to prevent variations in current due to internal mismatch causing those said variations.

When playing with very high frequencies, one gets into transmssion line theory, with the twist that the circuit board materials themselves were not fully characterised at speeds over 1GHz. There are interesting effects that have surfaced. Once I get back to the office (Wednesday it what that looks like right now) I'll pull the reports I stashed away. Looking at a PCB using S-parameters those effects become clear. One interesting thing is the delectric constant of ordinary FR-4 is not constant with frequency, so impedance controls must be viewed within a band of frequencies within which the dielectric constant is *fairly* constant.

I've seen the results myself of length mismatch, and it's quite measurable with a spectrum analyser and a cheapie (lab built) RF probe.

Truly differential signals are, strictly speaking, not coupled to anything but themselves. On a PCB they are related to ground, but not as closely as a single ended signal. Incidentally, the RF type term for these is balanced (diff coupled) and unbalanced (single ended).

Because ground is not necessarily 'ground' everywhere. At 1GHz, even a plane has significant inductance. This is one of the reasons we stitch planes at short intervals - to try and keep the potential equal everywhere on the reference plane. For a classic example of ground being a radiating element, we have only to look at a quarter wave antenna. A quarter wave antenna is one half of a half wave dipole, with the other half being provided by a 'reflection' from ground. Ground, in this case, is the signal reference, but radiation occurs between two elements - ground and signal in this case. That's a reason you need a ground plane of a certain minimum size ( 1/4 wave) to make a quarter wave antenna operate properly.

The effective impedance of a power or ground plane (when referred to chassis) can be quite high without local decoupling.

Hmmm. When we talk SI, I include my signal loss budget (of which length and impedance matching is a major part). Length mismatch equates to a signal energy loss when looking at a differential pair, and is easily calculated. If I have a length mismatch of 0.5 inch betweeen pairs, then a 1GHz signal pair will arrive at the destination 80 picoseconds apart, which equates to 28 degrees of mismatch. That will cause an effective loss of 13% in the differential signal (1-COS phase). The 13% now shows up as a common mode signal, and common mode signals are what radiate. The PCB losses due to dielectric absorption and skin effect can also radiate, but not as much. Forcing proper length matching minimises this effect. The tightest length match I had to do was in a DDR system, as it happens.

Another place to get losses is through vias, because they are not really matched to the transmission line. I did a lot of work to figure out how to do impedance matched vias a few years ago, and there's a white paper somewhere on TI's site about it now. I was successful, by the way, but only after a lot of hacking on a field equation solver :)

Impedance match (or lack thereof) causes radiation in the same way an antenna does. An antenna can actually be looked as a transimpedance device, matching the driver (50 ohm perhaps) to the characteristic impedance of free space (377 ohm).

Something that does not seem to matter is sharp corners on a transmission line (which some might definitely say is heresy but the data exist to support the conclusion).

This seemed to be very clear

E&M theory is complete as far as it goes, and for it's limits. As we push faster and faster, and denser we find corner effects that must be added into the theory to make it complete. Although E&M is dominated by things we know of, there are interesting effects we run into as we push circuitry into new and unexplored areas.

I use small parts because I have machines place them and they save me precious space. The size of coupling components _does_ have an effect on signal integrity (device parasitics are roughly proportional to device size), although up to about Gb/s 0402 seems to be fine. Above that, the parasitics start to noticeably degrade the signal. This is also partly due to pad sizes and the attendant impedance mismatch because the track width varies.

I do the calculations because I need to know where I really _need_ to focus my decoupling efforts. I agree that physically smaller caps don't make any real difference to impedances, but you can fit them in spaces larger ones won't go, such as between the balls of a BGA for _very_ close decoupling, which minimises inductance to the plane for a power pin.

I've had to add a component or two but so far I have not had to redesign a board for EMC (although it was _incredibly_ close on one occasion).

Simulation tools are wonderful; the issue is properly simulating the board. Was he using FR4 or a PCB material designed specifically for higher speeds that is more fully characterised for dielectric tangent and constants?

I didn't completely answer, but my better half is waiting patiently for us to go out for the day - I'll complete later.

It's an interesting and illuminating discussion.

Cheers

PeteS

Wait a minute. The unshielded transmission line is a loop. If the wavelength is much longer then the loop size then the loop radiates proportionally to the area of the loop.

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

I should have said:

A perfect transmission line that is terminated at source and destination in it's characteristic impedance will not radiate except into the terminators. There was one product I worked on many years ago that had a perfect quarter wave track with an imperfect match at the destination. Very interesting effects :)

Cheers

PeteS

But at $.008 per capacitor, how much engineering time is appropriate to design a circuit "right the first time". Admittedly, it may be important at ghz clock rates or where board space is at a tight premium, but for the majority of the folks here designing in the 10's of mhz, I think the old rule of thumb might be the more cost-effective method.

In the words of Tom West, "Not everything worth doing is worth doing well".

The external fields generated by the differential signals only cancel nearly completely, when the distance between the conductors is only a very small part of the wavelength. At least with open wire balanced feeders, the rule of thumb is to keep the conductor separation below 1 % of the wavelength, to avoid radiation.

Applying this to typical dielectric constants used in PCBs (and hence velocity factors) and a 500 MHz square wave (with significant power in the 3rd and 5th harmonic), the distance between the conductors should be less than 1 mm, to keep the harmonic radiation at very low levels. Maintaining this distance can be hard, if the differential outputs are not at adjacent IC pins or the balanced line contains sharp corners.

Paul

But when you properly design a PCB with a closely coupled ground plane, it is nothing like a differential signal on open wire. In fact you can treat the differential pair as just two signals that should have closely matched lengths to arrive at the destination at the same time. What is meant by "closely matched lengths" will vary depending on the person you ask. I say it is related to the edge rate. If you are closer than 1/6th of the edge time, you are doing enough to greatly minimize the EMI; that comes to about 1 inch for 1 ns of rise time. Of course the closer you match, the lower the EMI. Matching better than

1/4 inch should be no problem at all and should produce good results for most edge rates until you get to the really fast stuff.

Exactly. It depends on what you are building. Most of the stuff here is not really high speed, but it is handheld and we are always trying to shove 10 lbs into a 5 lb bag. Being able to drop a few dozen caps is nice even if they are only 0402s. There is also the issue of knowing that the job is done right. If you just sprinkle around a bunch of 0.1 uF 0402s, you likely still have an impedance hole at a few hundred MHz which may blow your EMI testing. Do it right and you can be confident that you can pass.

I only have a few minutes tonight, but this is interesting. One of my products is handheld (well, a large handheld for industrial apps) and it has a *lot* of stuff in it, so EMC is dear to my heart, especially for devices in plastic boxes ;)

I would agree it's easy to have a gaping hole because the system was not *properly analysed* prior to layout. I consider that analysis time well spent. Device placement, incidentally, is just as important, and here there are competing interests where it is not usually possible to satisfy all desires. The usual issues are thermal management vs. EMC vs. signal integrity / lengths.

Cheers

PeteS

When you put a PCB track above a continuous ground plane, you create a microstrip transmission line, in which most parts of the signal propagates as an electromagnetic wave in the dielectric between the conductor and the ground plane. Unfortunately, quite a lot of the field propagate above (in the air) or on the side of the connector and can thus radiate much more easily than in a completely surrounded stripline. Due to the escaping field, microstrips should have a considerable free space around and above the conductor to avoid impedance bumps.

If you put the differential strips close to each other (compared to the dielectric thickness above the ground plane), the main part of the electromagnetic wave will propagate between the strips, partially in the PCB substrate and partially in the air above the strips, with little external field. When using a large separation between the strips, the stray external fields do not cancel completely.

Paul

???? Unshielded transmission line will radiate even in the case if it is perfectly matched. BTW, there is a number of antenna designs with the running wave.

Sure. I have no doubt about it :)

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

Have you verified this with measurements? I think you will find that a transmission line radiates very little if it is close to the ground plane. It is not at all clear to me that the termination has much to do with it. An unterminated line simply reflects the EM wave back to the source which absorbs a portion of the wave in the source resistance and reflects the rest back. But this has nothing to do with radiating.