SI and EMI training

I just took a course in SI and EMI and I was very impressed with the instructor. He made the entire subject very simple to grasp. I feel like I can do my next board level design with virtually no doubt about meeting the SI and EMI requirements.

A lot of the class talked about so many "myths" that we as engineers have developed and seldom question. One in particular is the way that power supply decoupling caps are applied. I have seen this topic debated here and elsewhere with a *huge* divergence in philosophy. Few people were able to produce any info to support their claims other than that their board worked. In this class I saw a rational explanation of the approach along with theoretical calculations to back it up and finally measurements on boards to show that the theory was right. In the end I was very impressed and realize that most of my power distribution was either very overdone or in some ways marginally sufficient.

Anyone else had SI and/or EMI training that was similarly revealing?

Reply to
rickman
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Dream on. Youthful enthusiasm :)

The theory deals with the idealistic assumptions. In practice, it depends upon many unknowns.

Yes. It is nice to have the things arranged and explained just to know that my designs where done without any obvious flaws. Nevertheless I had to do a lot of EMC black magic in some cases.

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

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Reply to
Vladimir Vassilevsky

Can you put that in writing please..................................

martin

Reply to
martin griffith

We buy over 100,000 .1 ufd bypass caps per year and we're a tiny company. Can't use too many. That's all I know.

Reply to
Jim Stewart

That was the biggest misconception I had about power decoupling, that numbers were required. But once I saw the method and the rational behind it I am convinced that the "one cap per pin" rule is a myth.

That was the single most important point I got from this course, the fact that if you know *how* to design a circuit "right the first time", you can forget about rules and guidelines that have never been explained or proven.

BTW, the instructor is a consultant who has done hundreds of designs with clocks up to 4.8 GHz and higher. He claims success on every one of his designs and showed us many, many designs that went to production without a respin. He also related many stories of companies that did not do a good job of dealing with noise in high speed digital circuits. Mostly you would not know their names because they never got the product out the door. He knows about them because he was called in as a consultant and had to tell them to start over...

Reply to
rickman

Youthful, sadly no... enthusiasm, absolutely! I love it when I learn something new that I can use. I have pretty much covered everything there is in the digital domain and this is the first time I have learned from an expert about SI and EMI in these high speed digital designs.

They are only unknowns if you don't know how to deal with them. What unknowns are you referring to? One of the more important points that he made was that you can ignore physics if you want, but it still won't go away. If necessary, a test board can be built to measure any unknown in your design. This guy has built many test boards just so he could measure these sorts of things and be able to make statements backed by facts rather than speculation. I can't remember ever talking to someone who was in the position of being able to back up every thing he said with facts, both theory and measurements.

That is the point. "Black Magic" is what you use when you don't fully understand what is happening.

Reply to
rickman

I found this document, from Atmel Europe, very good. Quite old, but still valid, as the fundamentals do not change.

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Similar to what you describe, it includes real measurements, and plots SRF effects.

-jg

Reply to
Jim Granville

Doing RF design in the UHF or microwave bands for a few years is a good background for digital equipment PCB design. When you intuitively look at every PCB track as a microstrip or a stripline transmission line should help a lot in designing trouble free PCBs.

Unfortunately adding one or two extra ground plane layers into the PCB and/or using extra board area for transmission lines with proper impedance levels, might not be acceptable for high volume product due to cost reasons. For low volume products, I don't see why proper design is not done, since avoiding a few iterations in the EMC tests will save the extra cost of proper PCBs.

Paul

Reply to
Paul Keinanen

Good. The subject becomes less trivial when cost reasons make you do double layer instead of multilayer and when size and price becomes a guideline.

Rene

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Reply to
Rene Tschaggelar

I, like a number of others here, have done highspeed designs (my upper limit on copper is currently 5Gb/s) and although there is sufficient theory to calculate the number of bypass caps, in practice there are usually insufficent time and tools to use all of it.

A reason we have rules of thumb is that they usually work. Usually, of course, is a key word here ;)

Others could no doubt give you a real design, but here's one to chew on:

Consider doing a board with said 5Gb/s pairs (but make sure there are almost 400 such pairs) on a 16 layer board [constrained to that because of drill sizes available for breakout], where the devices with those signals require 4 different power supplies (an entire EMC/EMI issue in itself) and a backplane (or perhaps a cable) connector. Once you have figured out your routing (autorouters are worse than useless with these types of signals) and your via strategy (taking a signal of this speed through the board requires special care), you might find that there are so many variables that you simply sprinkle a few (make that dozens or even hundreds) extra caps into the thing.

This all ignores the other various control and status in the device (things like DDR memory and processors - you get the picture).

You might not populate them, but the positions are there for insurance, as are a bunch of ferrites and resistors. Considering we can fit literally hundreds of discretes in a square inch and they typically cost less than 10/cent in the quantities we buy in, such insurance is cheap.

Yes, it is interesting to see what the required decoupling is (and that's only part of a complete EMC strategy), but in practice there will always be some unknowns that there is *no time to solve* of you are ever going to ship your product.

It might be intellectually satisfying to know one has done the minimum required to get EMC at an acceptable level, but EMC is one of those areas where apparently innoccuous things can bite you.

I had a device (one of the x-point switches in the above design as it happens) that was flip-chip and had a hefty heat sink. The heat sink fins *just happened* to be 1/4 wavelength and operated as pretty damn fine antennae on the unavoidable differential to common mode converted signals in the area. That has little to do with decoupling, but extra decoupling of the device helped minimise the *internal* common mode conversion. I also had to find a different heatsink (not easy as I needed to dissipate lots of heat, but the enclosure limited the height of the heatsink) and adjust the forced air cooling.

So bear in mind that there are really good reasons we sprinkle decoupling liberally on designs ;)

Cheers

PeteS

Reply to
PeteS

He also showed some examples of high volume products which have to at least meet FCC part 15 EMI requirements. His method is to use a 4 layer board with power and ground closely spaced to the surface layers to get the right impedance. Since this puts the power and ground planes far apart the surface layers are flooded and used as the other half of the plane capacitors. The combination of close spacing to the traces and well decoupled power supplies reduces EMI from the board to acceptable levels.

The example he showed us was the 4 layer board designed for the X-box.

Reply to
rickman

Putting the power and ground close to the surface layers is a well known decoupling trick. I have put power and ground *adjacent* and near the surface a number of times, and it certainly helps (distributed capacitance, minimum inductance to the planes). A 4 layer board can have more control of layer distance than a much denser board, giving more options for decoupling.

It is part of an overall strategy; it's not a panacea.

Cheers

PeteS

Reply to
PeteS

Yes, the instructor mentioned this many, many times, ususally followed by the statement, "If you don't have time to do it right, do you have time to do it again?" He also had many examples of companies that called him in to solve a problem and he had to tell them to do it over. Some of those companies had blown their VC money and were not able to do a redesign.

He gave us examples with multiple high speed signals and he still used the same methods. One had 17 different power supplies and most had connectors in the high speed signal path. So I don't see where a complex board makes "rules of thumb" more important, but rather less important. The problem with a general rule is that it has to be qualified and no one remembers the qualifications.

I think that these sorts of general rules are used not because it is not important to know how to do it right, but because people don' t know how to do it right. I am always happy to learn how to replace a "voodoo" rule with a knowledge based rule.

Actually he used memory interfaces in his examples and even spoke of how DDR2 is not currently working. Heck, I remember that from SDRAM. They were making motherboards with it, but you frequently could not populate all the slots or it would only work with certain brands of memory which differed between brands of motherboards. This was an SI issue. With DDR2 it seems that the problem is just too tough to solve so they are going a new version which will buffer the signal on each DIMM and daisy chain the signal path.

I hear that a lot. Sure caps are cheap, but board space is not, especially on high layer count boards. Don't forget that every cap needs two vias which create routing congestion on all layers. The design methods he used don't take a lot of time, you just have to do them.

Can you give an example of some of these unknowns?

I'm not clear on how the decoupling caps helped here. I'm not familiar with the term "*internal* common mode conversion". If your power plane is well designed there will be very little noise to radiate. He did mention that to create EMI you needed two things; noise and an antenna. Signals on the board are not good antennas, so they don't radiate much. Your heat sink sounded like a perfect radiator at a critical frequency. You changed the heat sink, so how did the caps help?

I'm not trying to change everyone's methods of designing. But this class changed a lot of my thinking where I had been using these "voodoo" rules. Partly I am posting to inform others that these rules are not good or necessary and partly I am posting to find out what others are doing. You seem to be a designer who is happy using "rules of thumb". If you are interested, you might consider buying Ritchey's book, "Right the First Time, a Practical Handbook on High Speed PCB and System Design". I don't recall how much the class was, but I would certainly recommend it.

Reply to
rickman

It is not always known of what are the effective sources of the EMI on=20 the part and what is the path of the EMI currents. Take the datasheet on the =D1S42438 and guess how to connect it.

Also, is not always known what kind of wicked resonances does have the=20 board, since it depends on many factors.

The point I am trying to make is of course it is necessary to understand =

what is going on, however you will always have to do some EMC work,=20 no matter how good is the theory.

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

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Reply to
Vladimir Vassilevsky

Why would you have to guess how to connect a part? I have not looked at this data sheet, but if it is incomplete, why wouldn't you ask the vendor to complete it?

What would be the source of resonances in the board? The examples shown in the text book for this course show that the impedance of the power planes is capacitive up to the point where a quarter wave length spans the board. Then it develops resonances at 1/4, 1/2, 3/4 and 1 lambda. This will be at very high frequencies unless your board is very large indeed.

That is what I am trying to understand. I saw data from a number of different tests and real boards. There is no mystery to the design. If you have antennae on your board, then you may have special issues to deal with. But a normal board can easily be designed to pass standard EMI testing. What are you saying can cause problems?

Reply to
rickman

The datasheet does not seem to be bad. Take a look, and then let me=20 know, how you would do the design with that part.

Very little help. The app. engineers know no more then what is already=20 written in the datasheets.

This is in the blue sky theory only. The resonances are influenced by=20 the housing, the geometry of the planes, the cuts and the holes, ground=20 connections, etc. The board resonance can be anywhere from VHF to PCS=20 band, which is not that high. BTW, the one inch of the track + 0.1uF ceramic make a nice LC at about=20

50MHz.

d

The antennae just happen to be. FCC Class B is not a very big problem,=20 however CISPR 25 is more difficult.

What is your definition of the "normal" board?

There is no wonder to do a design with microcontroller with everything=20 on the chip running at several MHz which satisfies the EMC. Typical designs that I am dealing with include a DSP system running at=20 hundreds of MHz and/or a powerful PWM at several hundred kHz. Although a lot of care is taken, sometimes the board has to be=20 redesigned several times for the EMC purpose.

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

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Reply to
Vladimir Vassilevsky

I could not find it. I searched using Google.

I guess this is an easy one, I wouldn't use the part. If I have a project, I don't want to have to guess at how to use a part. I just got Atmel to add crystal requirements to their data sheets on the SAM7 ARM devices. I had just worked on a design that had very specific requirements for the crystal to work with a TI clock chip. I learned enough from that to realize that without a clear set of requirements picking a crystal is just a crap shoot. If they had not come up with the data I would have dropped the part and gone with another vendor. Oddly enough they still did not properly spec the crystal and I had to come back with specific questions to qualify the crystal I wanted to use. They specified ESR and power level at specific frequencies rather than for the ranges of frequency. So in between the specified frequencies you don't know whether to use the higher or the lower value. Why can't they see that as an issue if you want to optimize your design? If you have to go with the lower ESR value you are limited in how small a crystal you can use.

I listened enough to the instructor to have an idea of how he would reply to your comments. This is what impressed me the most about him. He kept everything very simple and did not involve factors that could not be shown to demonstrate an effect. So many times someone would object to something he said and the reply would be "Why are you speculating?"

I don't believe a properly designed and connected housing would have any effect on the resonance of the power and ground planes. The spacing of power planes should be on the order of 5 to 10 mils so a housing a quarter of an inch away should have no measurable effect. If it does, it is pretty clear that it is not connected properly.

What capacitor and track are you referring to? One of the things I learned was that power capacitors (as well as chips) should never be connected by traces. The via should be immediately next to the pad with no trace and connected to the power/ground plane, not the chip. Then the planes provide a very low impedance path with a resonant frequency only related to the distance. This puts it up in frequency well beyond the SRF of the cap itself. He had a test board that showed very little difference on the effect of the capacitor between less than an inch up to about 9 inches from the measurement point.

Most of the things I have heard about these issues were speculation. In this class *everything* was illustrated profusely with theory, calculations, simulations and measurements on test and real boards. It left virtually no room for doubt, unless you think the measurements were just an example of things working right in spite of being designed with wrong principles. I say that because with power distribution, I expect that happens a lot. If you use enough decoupling of the wrong method and your requirements are not too high, nearly any method will work. That is why so many people use the shotgun method.

I understand. The goal would be to not have an antenna on the board or if you can't avoid one then make sure it is not coupled to the noise.

I have not done a single design to the principles I learned in the course. But in both of the cases you described the methods apply and have a lot to do with defining exactly what will be required and how to solve the problems before you design the board. If you say it is not possible to understand how the design will work in regards to EMI and SI, you will have a self fullfilling prophecy and you can expect to redesign boards multiple times. This instructor demonstrated very clearly that this is not required.

BTW, in this case "normal" designs include everything you mentioned and many more difficult designs. The instructor has been designing boards for some thirty years and claims to have never gotten it wrong on the first try. He received a call during class and announced that it was about a problem that may be his first failure on the first pass. The next day he said it turned out to be a measurement error... That gives me a lot of confidence in what he was saying. Of course you can argue with the accuracy of his claim since there is no way to verify it, but once you met the guy, I am pretty sure you would not doubt him. He just is not the egotistical type that would care enough to lie about it.

I just wish the designs where I work had need of testing his claims. But unfortunately we don't really do much that is truely high speed. Yes, we do DSP designs at hundreds of MHz, but they aren't hard. The external busses are only 16 or 32 bits and not so fast at 100 Mhz. Even our FPGA designs require very little from the boards they are on. But these principles will let me design to minimize EMI and that can be tested on my designs.

Reply to
rickman

You obviously live in an ideal world where no datasheets have missing or wrong details, where the points of contact with the manufacturer know all aspects of the design of the part and its use.

Most EMC/EMI testing is SYSTEM related, not just board related. Other variables come into the equation, which the maufacturer of the part being used is not aware of. An example being the variable loadings of fluorescent tubes for a particlur lighting controller I once saw, where the characteristics with age/temperature/frequency could change dramatically! This could only be tested with a WHOLE system, not a board and even then how the cables are run can make a difference as well as type of screws for the casing or their spacing can also make a difference. Examine a microwave oven and see how many screws that has around its case compared to a TV set.

Like most physics principles, physics relies on removing all other variables to look at one particular aspect. Like the old joke about "spherical horses in a vacuum".

I would like to know what BOARD you would put through EMI/EMC (they are different) testing and how it would be tested as a BOARD, as most testing is done on a SYSTEM in NORMAL use.

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Reply to
Paul Carpenter

No, I live and work in a world where the laws of physics apply and if I can't get accurate information from the manufacturer of a device, I have no idea how to use it and mostly don't try. I have been burned before by bad chips and will never use a device that I can't get an eval board for so I can verify the operation if the application is critical.

nt

That may be true, but it is not relevant to the question being discussed. If EMI comes from a system and the board is designed properly, then something else in the system is causing the EMI. If the load varies with age, then you have to design the board to take that into account. If you fail to consider this, then your design will fail testing. Where is the mystery?

Yes, and then you apply the principles of physics to your design as simple or complex as it may be. If you think your design is too complex to analyze, then you can not expect to get the behavior from it that you desire. It is that simple, either understand it before you design it, or live with the consequences.

I never said I would test a board separate from the system. But clearly if you design the board to minmize radiation then it will minimize your problems with EMI of the system. You also have to design the interconnect and apply adequate filtering to prevent external connections from radiating. Of course this may not be easy, but what other choices are there? Radiation requires two things, noise and an antenna. Remove either of these and you won't have EMI. If all else fails you have to provide a Faraday cage.

I don't want to argue about systems anyone has designed or the problems they had. My point is simply that there are some very simple techniques to minimize EMI and provide adequate SI when designing boards and systems. I learned a few techniques that seem to be very simple to apply and have a strong base in reality in all respects. When someone tells me he has designed a large number of systems with no failures on his part, I believe that his methods are sound. You can work any way you wish.

Reply to
rickman

Translation

I have been on a course and have been given the latest mantra I then ask people to discuss I then just answer points by reciting points from the lectures without working it through to explain the answers having of course not actually read the points raised correctly.

.....

The mystery is how the hell you expect to predict EVERY aspect of the design and ALL potential problems with components, before using them when the manufacturer may not even be aware of a problem. How many people these days even consider the ageing aspects of components for time periods less than 1 year? The answer very very few, because it rarely affects them.

Every component is potentially part of the problem and part of the solution.

The mystery is your perfect crystal ball.

I suggest you do some research on that joke then come back.

When you understand the point come back.

You cannot prove a negative, therefore to PROVE you have designed the board to meet EMI you would have to test the BOARD.

Radiation requires the third thing which you have forgotten

Sufficient energy to cause an antenna to radiate[ 1 ] to a measurable amount in the bands to be measured in.

[1] Most EMI tests for CE and consumer goods are based on causing interference to analog TV's at a predetermined distance, then working back from that to get the field strength required.

You saw examples of techniques on special test cases, to prove specific isolated test cases, to prove isolated examples on isolated problems.

You sound like you are personally trying to promote the course.

Are you on commision?

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Reply to
Paul Carpenter

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