What is the DSP architecture of the SHARC? - RM
- posted
19 years ago
What is the DSP architecture of the SHARC? - RM
What is the DSP architecture of the SHARC?
Specs are Harvard architecture + * 32/40-Bit IEEE Floating-Point * 32-Bit Fixed-Point Multipliers with 64-Bit Product * All Computations Are Single-Cycle * 32 Address Pointers [pairs?] Support 32 Circular Buffers * Six Nested Levels of Zero-Overhead Looping in Hardware [sweet] * Algebraic Assembly Language Syntax * Instruction Set Supports ... Bit Field Deposit and Extract * DMA Zero-Overhead Transfers at Full Clock Rate [sep.bus]
What's it best at? worst? - RM
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