SDRAM (MT48LC8M16A2) interfacing problem with AT91RM9200 :-(

Hi,

Im trying to interface a 128Mbit SDRAM (MT48LC8M16A2) to the AT91RM9200, but it doesnt seem to be going right. I dont have any sort of debugging aid xcept the debug unit connected to the serial port of my PC, thats how i send the program in. The Master Clock is running at about 60MHz (~16us time period).Heres the program that im loading in to init the SDRAM: ==================================== void AT91F_InitSDRAM() { int i; int *pSDRAM = (int *)BASE_EBI_CS1_ADDRESS;

//* Configure PIOC as peripheral (D16/D31) AT91F_SDRC_CfgPIO();

//* Setup MEMC to support CS1=SDRAM AT91C_BASE_EBI->EBI_CSA |= AT91C_EBI_CS1A; AT91C_BASE_EBI->EBI_CFGR = 0; //Active high DQs

//* Init SDRAM

//Values taken from the SDRAM Manual:Cols=9,Rows=12,CAS=2,TWR=2,TRC=5,TRP=2,TRCD=2,TRAS=3,TXSR=5

AT91C_BASE_SDRC->SDRC_CR=0x29912955;

//* 1. A NOP is provided //testing only, consider removing

AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_NOP_CMD; for(i=0;iSDRC_MR = AT91C_SDRC_MODE_PRCGALL_CMD;

AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_RFSH_CMD; //* 3. Three Auto-refresh commands are provided, the RAM manual asks for 2, the atmel manual asks for 8 for(i=0;iSDRC_MR = AT91C_SDRC_MODE_LMR_CMD; for(i = 0; i < 100; i++);

//* 6. A Normal Mode Command is provided, 3 clocks after tMRD is set AT91C_BASE_SDRC->SDRC_MR = 0x0;//Burst length=1

//* 5. Write refresh rate into SDRAMC refresh timer COUNT register AT91C_BASE_SDRC->SDRC_TR = (AT91C_SDRC_COUNT& x200);//4096 refresh cycles every 64ms, ~384, changed to debug

} =================================================== To test the RAM is ready, i do the following: =================================================== volatile char *base = (char *)0x20000000; volatile int *base2 = (int *)0x20000000; char buf[10];

sprintf( buf, "%x\r\n%x\r\n", *base, *(base+1));//printing the last and second last byte(little endian)

AT91F_DBGU_Printk( buf ); sprintf( buf, "%x\r\n", *(base + 1));//last byte again..see what happens.. ==================================================== Since im testing the code through HyperTerminal, this is what i see: ==================================================== dd cc ff ==================================================== and all subsequent accesses to the 4 addresses shows ff (the data lines are pulled up, thats where the ff is coming, i thnk..) This happens every time..whatever ive written on the RAM vanishes when i access it a second time..seems like a problem with the refresh..a guess, anyone, or a problem with the code?? Thanx in anticipation, Mayank