Samsung DDR-behavioral model

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I have a problem when simulating with samsung ddr behavioral model, I
have tested my design with micron behavioral model but micron is not
accurate regarding the tDQSS time constraint. so I used the samsung
model, but I don't know why the DQS bus in write transactions goes to X
state. it seems that the behavioral model tries to force on the DQS
while the controller tries to force on the DQS. so the result goes to X
state.
I am not sure, my design is in VHDL and the samsung model in Verilog I
uses ModelSim 5.5e PLUS to do the simulation
I dunno where is the problem, can anyone help?


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