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RTC problem (reading all zeros)

Using M41T81S, VCC=3V3, 1k pull-ups, with AT91SAM9260. VBAT is connected directly to VCC.

I've zipped (almost) complete sources and a GIF. GIF shows what I *think* is happening. Yes, something else *might* be happening, but the code is so simple...

Code reads registers 00-13h and they are all read as zeros. Code checks for ACK from RTC - it is always zero. The line is not stuck at zero, however. I've checked with a crappy instrument just if my signals get to the chip - they do.

There are breakpoints (BKPT) in the code - which never triggers.

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Reply to
aleksa
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I forgot to mention that the SDA graph in the GIF file is valid only in START and STOP states.

At other times, I just toggle it all the time.

BTW, I read everywhere that i2c requires pull-ups on both lines... why? So that there can be multiple masters? In case there is only one master (the CPU) and one or more slaves, I could remove the pull-up from the SCL line, right? i.e. no open-drain output. I am new to i2c, but I guess only the master drives tre SCL line.

Reply to
aleksa

When outside of a start/stop both lines should be high due to pull-ups. No toggling - where did you get that from?

SCL and SDA are both open drain, to be standard conforming, so you must have a pull-up on both lines whether it's single- or multi-master. The chips don't do this themselves because they don't know how many devices will be on the bus, the bus length or speed.

Peter

Reply to
Peter Dickerson

toggling - where did you get that from?

The graph represents the behaviour of the RTC_read(), start, write, write, start, write, read, stop.

The graph shows what I expect on the lines, with regard to the source prog. Again, SDA data shown for read/write/ack is imaginary.

pull-up on both lines whether it's single- or

many devices will be on the bus, the bus length or

Reply to
aleksa

Not true in the general case. SCL should be an open drain driver with pullup according to the specification.

Some slave devices will retard the master by yanking low on the SCL line when it is low. This is normally referred to as "clock stretching" and if the master does not comprehend this and uses an active pullup driver on SCL you end up with signal line contention for the duration of the stretch.

Only good thing going here is that only some slave devices do clock stretching.

--

Michael Karas
Carousel Design Solutions
http://www.carousel-design.com
Reply to
Michael Karas

That info saved the day.

The original code (in the zip file) was testing for this, but it didn't work for me, the code was stuck waiting for SCL to go high, so I have foolishly removed it.

Why was it stuck? Because AT91SAM9260 has a clock enable for PIO. If the clock is disabled, you can't read the actual pins.

Thanks!

Reply to
aleksa

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