Routing signals under crystals

Hello,

We got a product that uses a low power RTC crystal and a 12Mhz crystal on a 4 layer board. The inner layers are VCC and GND. Should I remove the VCC o r/and GND under any of both crystals? Would be a problem to route or place any component on the oposite side of the board? Currently I am removing the VCC layer under both crystals and leaving the GND layer under the 12Mhz cr ystal to improve shielding but removing under the Low Power RTC Crystal to avoid unwanted capacitance. Is that correct? If yes, considering that there is a GND layer under the 12Mhz crystal, would be a problem to route any si gnal or place components at the oposite layer?

Best regards,

Luis

Reply to
Luis Filipe Rossi
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"Correct" is kind of hard to identify, since you haven't stated exactly what you're aiming for.

The VCC layer will appear as an AC ground, so will also make capacitors from the crystal leads to "ground" if it's under the crystal pads. That's not necessarily a bad thing unless the RTC clock accuracy is a big issue -- if it is, then the two impacts that you should worry about are signal injection from VCC, and the capacitance changing (FR-4, apparently, has crappy temperature effects when used as a dielectric).

If I left any layer under the crystal pads, it'd be ground, and I'd make sure it was a quiet sort of ground.

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Tim Wescott 
Wescott Design Services 
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Reply to
Tim Wescott

Generally, you would want the crystal, and its bias network and interconnect over an isolated ground plane that connects to the rest of the ground plane at a single point near the ground reference of the oscillator. You do want to double check the datasheets for the crystal and oscillator for guidance (i.e. is the parasitic capacitance an issue like you mention.

I would then put a similar isolation on the VCC plane to minimize noise coupling, or even make it an additional isolated ground plane.

Now, since you have a plane cut here, you do not want to cross that with critical traces (either high speed or high power) to avoid the break in the reference plane. You can probably allow yourself to place low frequency/low power circuits on the other side of the board here.

Reply to
Richard Damon

In the days of free running VFOs, it was a common practice to remove any ground planes from the opposite side of the PCB. The reason stated was that the PCB material is hygroscopic and the stray capacitance (and hence frequency) varied with humidity.

The problem of removing any ground plane is that the electric field extends below the PCB and now the distance to a metallic box affected the capacitance. Any flexing that changed the distance could cause drift and/or microphonics.

For a crystal, you can tune a fundamental crystal by a few hundred ppm by adding a capacitor. The sensitivity is less than a few ppm/pF, thus thermal expansion or humidity effects should not vary the crystal frequency very much.

Reply to
upsidedown

I usually design 4 layer boards with stacked like this:

components signal layer ground plane "power" plane signal layer (possibly more components)

I don't remove ground under the crystals because I would rather shield the crystal from em radiation and the world from hf noise. If I want a stable clock I would use a ready made oscillator for HF. Low power RTC crystal oscillators using external crystal are quite susceptible to radiated em interference.

I'm unconvinced by little areas of isolated ground plane with single point links to big ground planes - works great at 50Hz or even 32kHz but useless at 1GHz.

I rather think that since we all have different opinions it may not actually matter that much.

Michael Kellett

Reply to
MK

I would agree with you though I tend to flood ground on the top and lower layers to bolster ground. Also the last thing I would want is a hole or slot in any ground so my grounds would be continuous wherever possible.

I might add that my thoughts are that interference would cause jitter rather than a shift in long term frequency. If, as I suspect, these crystals are attached to a micro, then I suspect the grounds in the IC are going to be moving around far more than any PCB ground.

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Mike Perkins 
Video Solutions Ltd 
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Reply to
Mike Perkins

Thank you for the help.

The microcontroller is a MSP430 and I do care about timing precision of the RTC, but for sure it do not need to be an atomic clock. It is a 20ppm crys tal, so if I can keep it within */-2sec/day drift it is acceptable. I am us ing MSP430 internal capacitance and MSP430 RTC internal trim to reduce the capacitance mismatch.

In fact I was double checking the last board version and I was already plac ing a ground plane under the RTC crystal with a single point connection to the remaining plane (Not sure why i was considering no plane at all). Still .. should I keep it as it is or make it a solid ground? Should i place the VCC plane?

Regarding the placement of components in the opposite side of the board. Th e only component that I believe would be problematic is a piezo buzzer (wit h max current of 3mA). What do you guys think? Should i keep it far from th e RTC crystal, or 3mA is just too low....

Thank yoiu for your help.

her

Reply to
Luis Filipe Rossi

That's why I asked the OP what his needs were -- your "not very much" may be his "way too much". Of course, if it is then his "way too much" may mean that he's taking the wrong approach.

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Tim Wescott 
Wescott Design Services 
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Reply to
Tim Wescott

Ok, here is another country heard from...

I think the purpose of the isolated plane with a single point of attachment is to minimize capacitive coupling of noise caused by ground plane currents. Personally I expect that you will never be able to measure these effects in an MSP430 design unless you are switching relays or have some *very* fast edge rates on other circuitry.

If you expect to see a benefit to the isolated plane, the ground for the oscillator in the MSP430 will need to be at the same potential as the isolated ground. Does the MSP430 even have a separate pin for the oscillator ground? If not, all the grounds would need to be at the potential of the isolated ground.

I expect this is an exercise in diminishing returns. Why try to solve a problem you don't have? Keep noisy signals away from the crystal and the traces to the oscillator. Otherwise I expect you won't need to restrict the layout any further.

Rick

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Rick
Reply to
rickman

I also built an MSP430 design that needed such a clock. For best accuracy, you need to compensate for temperature. The xtal manufacturer should be able to provide temperature curves, or you can match them. Crystals slow down either side of their design optimum temperature, on a basically quadratic curve, so if you can sense temperature, you can measure three points and solve the quadratic to get the curve parameters that match your crystal.

Keep the loop area small by running both leads to the piezo close to each other and you should have no problems.

Clifford Heath

Reply to
Clifford Heath

Just one comment. When you say "crystals" have a quadratic frequency response vs temperature, that should be X cut crystals which are typically used for the 32.768 kHz oscillator. AT cut crystals which are typically used for MHz frequencies have an S shaped response (an S on its side). They can be cut so that the shape of the S varies from a true S to a line that is more of a double curve with a 0 slope at room temperature.

I think a 3 mA buzzer is not a real issue as long as it isn't *close* to the crystal leads. "Close" means passing directly under the crystal package or leads, especially in parallel. There is very little coupling between traces running parallel on the same layer on low impedance traces, but then a crystal isn't really a low impedance circuit so I guess even on the same layer parallel traces should be avoided.

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Rick
Reply to
rickman

Or, dynamically calibrate against some other "better" reference. E.g., I almost always implement a line frequency clock (LFC) in mains powered designs. It lets me monitor power availability (i.e., impending failure) as well as providing a reasonably stable (long term) time base.

Very helpful for syntonous sampling of signals that are influenced by noise sources associated with the mains.

[And, for products that support battery backed *operation*, it let's you know when you're running off that backup]
Reply to
Don Y

The purpose of a semi-isolated ground plane here is not to establish a star ground (which can be useful to fight low frequency ground loops), but to exclude high frequency energy on the ground plane return from getting near sensitive circuits. For a micro-processor clock, it may well not really be needed unless you have a nasty signal traveling on your board, but many design notes still ask for such treatment, and if it doesn't cause other layout issues is still a good goal to try to meet.

Reply to
Richard Damon

I use this same stackup and don't bother with changes to the ground plane.

I also don't worry too much about the stability of 32KHz crystals--- especially given their ~25PPM/ deg C temperature coefficients. For better long-term stability and accuracy, I use a DS3232 temperature compensated RTC chip. It's pretty straightforward to synchronize the internal RTC on a micro to the output of the DS3232 either by using the 32KHZ output directly or by phase locking the micro clock to the 1Hz output of DS3232. The improved stability and accuracy are really helpful when trying to track events through an array of moored instruments that have been sitting under a hundred meters of seawater for a year.

I agree with that. It's probably even less of a problem when the fastest clock on the board is in the internal processor of the SD card logging the data. Writing to an SD card can generate quite a burst of EMI, but I haven't seen large effects on crystal behavior.

Mark Borgerson

Reply to
Mark Borgerson

What if the PSU is on one edge, the buzzer is on the opposite edge, and the crystal+MCU is in between? :)

Sensible? No. Possible? Yes. Never underestimate the ability of people to do silly things :(

Reply to
Tom Gardner

Good to know, thanks for the extra detail. I hadn't done any high accuracy stuff with AT cut xtals.

Even a small mechanical shock can make an xtal osc go squirrelly for a bit, so the less of all kinds of impulse the better. I.e. 3mA isn't the issue, rather it's the edge speed. An MSP430 output may have

100 ohms impedance (I did this a long time ago, perhaps they're stiffer now) and the piezo has a significant capacitance, so you really shouldn't have a problem with the edge speed.
Reply to
Clifford Heath

Why would that create a problem? Remember, we are only talking about 3 mA currents. I don't think this will create a significant voltage on the power/ground plane, so I wouldn't worry too much where they put the parts.

I am talking about routing the traces away from the oscillator traces and crystal.

There are plenty of things they can do wrong. I had a design once that has an intermittent buzz in the audio. Eventually it was traced to 10 mV of 300 Hz noise on the power plane. Although adding more bulk capacitance would fix it, this wasn't from the board itself, it was from using poor power distribution *to* the board. The software cycles of the CPU caused variable voltage drops on the lines to the PSU which were not attenuated by the audio circuitry. I had used a POTS interface chip from CP Clare which had 0 dB of power supply rejection ratio. So 10 mV of noise on the power resulted in 10 mV of noise on the phone line!

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Rick
Reply to
rickman

Really? I've never seen significant EMI directly generated by any chip. The problem is normally the power distribution to the chip giving off the EMI. Is that what you are talking about, the power distribution to the SD card? Or does this come directly from the card itself? I suppose the PSD on the SD card might not be up to snuff.

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Rick
Reply to
rickman

Depends entirely on the edge rate and the inductance, of course. Not knowing either I can't comment on whether it will create a problem.

And the rise/fall time? And the mutual inductance of lines some of which feed a high impedance node?

The devil's in the details of course. Since the question was raised in a very general non-specific way, I'm not making any assumptions about the author's knowledge nor that of whoever laid out the PCB.

Reply to
Tom Gardner

The conversation is about an MSP430 and a piezo buzzer. These components would not create the fast edge rates that might cause a problem.

Did you read the full conversation? The mutual inductance would be determined by the geometry of the traces which is what we are talking about. There are also the capacitive effects which I believe is what dominates in a high impedance circuit.

Well, then it is impossible to give any useful advice other than, "Design carefully".

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Rick
Reply to
rickman

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