regarding full duplex in SPI protocol

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Hi all,

I am a newbie to SPI protocol.I have a basic doubt in SPI protocol,
since SPI is a full duplex(i.e it can transmit and receive
simultaneously),can anybody suggest any application wher both the
transmitter ande the receiver are both
active at the same time.

From my understanding SPI is used to configure some of the chips
through the  host processor,the miso pin is never used in this
application(assume no ACK's).

Can anybody clarify this.

Thanks in advance ,

Re: regarding full duplex in SPI protocol
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Your understanding is basically correct and your confusion is
As you say, some devices are essentially write-only.  You send them data and
you get no direct feedback or acks.
We use SPI as a simple but fast communication scheme between two processors,
yet only one has direct control of the SPI bus.  The master relies on the
slave to have it's data ready in a timely fashion.

Consider startup where the slave is not ready.  If it preloads the SPI data
with a value that indicates that it is not ready to receive commands, then
when the master sends a first command, it will simultaneously recieve the
not ready value.  The master must know to resend the command until it gets a
ready value.

When performance is at a premium, depending on how your slave data is
produced, you might double buffer the slave data.  Have one buffer
containing complete ready to go data and a second buffer that is being
filled as data is calculated.  The slave would put a preprocessed byte from
the buffer into the SPI register every time it gets an SPI interrupt when
the master sends a byte.

From personal experience I would also strongly suggest that you make your
spi code robust enough to handle error conditions.  It the master or the
slave isn't getting data that it likes, it must be able to resync somehow.


Re: regarding full duplex in SPI protocol
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That's what the SS line is for, no? Deasserting SS should abort a
multibyte transfer in process.

Re: regarding full duplex in SPI protocol
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Yes and no.  It really depends on the SPI implementation on the chip you are
using.  Only the master can deassert SS.  Some processors I have used do not
generate an interrupt on SS state change.  You can poll for it, but that is
another complication.

Also, if the SPI go out of sync from noise, I have used at least one
processor that does not recover cleanly using the SS line.


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