Ram disks/interfacing to commodity memory

I'm considering a project here where I'll need a reasonable amount of storage in an otherwise "small" system. The spec hasn't been firmed up yet but I imagine we're looking at a 16 bitter CPU, probably a PIC18 or an MSP430. "Reasonable" storage in this context means no more than 100MB. Volatility isn't a problem but the rewrite cycles are such I'd be wary of flash storage, so I'm finding myself drawn towards a RAM disk - i.e. not directly addressable memory but something that can be accessed after the requisite port set up.

Looking at memories the pricing of commodity DDR2/3 DIMMs are certainly very attractive but I'm a little hesitant over the interfacing requirements - I'm used to operating at a few tens of MHz, no more than double-sided PCBs and I know next to nothing of transmission lines. Can these memories be underclocked to that extent and still behave nicely, or does anyone have other insights?

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Andrew Smallshaw
andrews@sdf.lonestar.org
Reply to
Andrew Smallshaw
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DDR has a pretty high minimum clock rate, unfortunately. Regular SDRAM does not, but you still have to maintain a sufficient refresh rate.

How about using a CPU with integrated DDR interface ?

Reply to
Arlet Ottens

Duh. An integrated DDR interface still requires high speed PCB design.

How about using an off-the-shelf processor module with memory included ?

Reply to
Arlet Ottens

You'll need a dedicated controller to interface to DDR. What you can or can't do depends on what's available for the processor you choose.

SFAIK, you'll then want to use DDR as main memory, not as an expansion store.

Base your design on the eval board for that processor, including the BSP for the eval board. You'll need to spend some time testing access to DDR.

-- Les Cargill

Reply to
Les Cargill

DDR needs a lot of care and feeding, and because it's dynamic RAM it forgets what you tell it if you don't refresh it often enough. This means that you _do_ have a minimum clock speed that you can't go below, and that clock speed is going to be a pretty significant fraction of the highest permissible.

I don't have a clue if it's even available, but if you can find just about any kind of static RAM that should be much easier.

If you can't, you may find that the cheapest available DDR controller comes attached to some flavor of 32-bit processor.

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Tim Wescott
Control system and signal processing consulting
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Tim Wescott

Den l=F6rdagen den 7:e juli 2012 kl. 20:20:57 UTC+2 skrev Andrew Smallshaw:

Why not a SRAM 128k x 8 or 512k x 8 ?

Reply to
lennart.lindell

We'd be talking hundreds of chips to get the required capacity. I think some off the shelf board is going to be the answer here but I'll have to have a good look around for something that fits the form factor - I'm constrained in width more than anything else. The space available is approximately 10"x3"x1.5".

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Andrew Smallshaw
andrews@sdf.lonestar.org
Reply to
Andrew Smallshaw

A lot fewer of these:

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No Price !! If you have to ask......

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Memory Size 36M (2M x 18)

but:

Package / Case 165-LBGA

Reply to
hamilton

There are a number of manufacturers of pseudo-static RAMs, which basically do what you want - all the refresh and DRAM controller stuff is built in, and there's a simpler system interface. Micron makes several semi-close to size range you're talking about (128Mb - note mega*bits*), for example. Winbond makes some 256Mb versions. Try searching for PSRAM or PSDRAM.

No personal experience with any of these.

Reply to
Robert Wessel

128 MiB would be 16 MiW (64 bit) requiring 24 address lines, thus 12 column lines and 12 row lines multiplexed together.

At least older DRAMs will retain the data for several milliseconds (depending on temperature), thus each column should be referenced within that time frame. With 12 column address lines and 4096 columns, a refresh frequency would be about 1-2 MHz to refresh all columns.

Refresh is only needed, if all column are not accessed within these few milliseconds, any ordinary read access will refresh the whole column.

If a block oriented storage system is used with 4096x8 = 32 KiB pages, By reordering the address lines before the address line multiplexor, bytes 0..7 for each page would come from column 0, bits 8..15 from column 1 and so on, thus a single page read will refresh the whole memory. Thus, if there is a read access to any page within a millisecond or two, no extra refresh would be needed.

This tricks was usable at least with traditional RAS/CAS DRAMs, I am not sure if some DDR parameters would prohibit this.

Reply to
upsidedown

Den s=F6ndagen den 8:e juli 2012 kl. 03:09:06 UTC+2 skrev Andrew Smallshaw:

e:

w:

Sorry, too late at night, the brain was already switched off ...=20

Reply to
lennart.lindell

About the only way you can do this with a small processor is to use an FPGA with an SDRAM. SDRAMs can be seriously underclocked and if you use an optimum pinout on the FPGA you can route the FPGASDRAM interface on one side of the board - no funny stuff (eg matched track lengths or terminations) needed. The processor can access the RAM via the FPGA using any interface you like - SPI, //, serial etc etc. The FPGA task is not that demanding so it need not cost too much.

I know that all this works because I've done it (in more than one design). If you want detailed help contact me by email (which you can get via my web site

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Michael Kellett

Reply to
MK

I second lots of other people's answers re: SDRAM over DDR.

But this part's interesting: "Volatility isn't a problem but the rewrite cycles are such I'd be wary of flash storage". So it's not obviously dealbreaking, just worrisome. So what about a LOT of flash?

Digikey will sell you 8Gb NAND flash chips for about $16. Wear leveling

100Mb over that gives you another factor of 80 overtop the native 100K cycles. That's a whole lot of ins and outs.

Or possibly some interchangable storage, like an SD card, that you simply replace every now and again.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.
Reply to
Rob Gaddi

DDR memory requires fast signaling and basically always a memory controller. In one project we used Micron Mobile SDRAMs that have a self-refresh functionality. A quick search from Digikey gave MT48H4M16LF as an example.

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Mikko
Reply to
mi

What about a AVR32UC3 device that has an internal SDRAM controller? We use one of those running at 20Mhz along with a 64MB SDRAM from Micron. It's a 32 bit CPU but who cares, it's low power.

Reply to
certsoft

What do you mean by this? That they still work with a clock speed that is substantially below the maximum specified speed?

Groetjes Albert

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--
Albert van der Horst, UTRECHT,THE NETHERLANDS
Economic growth -- being exponential -- ultimately falters.
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Reply to
Albert van der Horst

Yes - sorry perhaps not perfectly clear - I'm not advocating running them outside spec but just making use of the fact that the minimum clock speed is very much lower than the maximum. This is not the case with DDRAMs where the slowest specified operating frequency is still quite fast.

Michael Kellett

Reply to
MK

Andrew DDRx memories use SSTL logic levels and require lots of understanding to ge= t right. Because they are double data rate they have PLLs within, hence the= need to go at a minimum speed to keep them locked. They are also BGAs. SDRAM is 3v3 CMOS and you can put them on busses with any other stuff and g= enerally abuse them. They don't have to be BGAs. I presume that you plan to= interface via a CPLD because your PIC18 or whatever certainly won't do it = directly. If you choose something like a MAX2 you wouldn't need any new pow= er supplies but they are BGAs.

Colin

Reply to
colin_toogood

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