question: interrupt nesting

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hi folks,

 I'm experiencing some problems on a Renesas M32C:

 it seems that a higher priority interrupt can't interrupt
 a lower priority one.
 To be honest, the datasheet doesn't anything about
 this thing, so I assume that it is impossible for this
 CPU to interrupt a lower priority interrupt to
 serve a higher one.

 My question is:

 can CPU's interrupt a lower priority interrupt to serve
 a higher one?

thanks
 Enrico


Re: question: interrupt nesting
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I am not familiar with this CPU, but on most CPU's interrupts are disabled
on entry of the handler. So you have to re-enable interrupts as soon as
possible, preferably *after* 'removing' the reason for the current
interrupt. I once made the mistake on an AVR to re-enable interrupts in the
handler for the serial port, *before* reading the received byte from the
UART...... endless waiting.......:-(

Meindert



Re: question: interrupt nesting



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Hi Meindert,

 yes! your right! I've just fixed this thing.

 thank you
  Enrico


Re: question: interrupt nesting
Been there, done that !!!  Pain is indeed a wonderful teacher.
Glad to see others do it the same way.

--
Mike "mikey" Fields
http://home.comcast.net/~mike.fields /
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Re: question: interrupt nesting
Enrico,
it will be the same as with the M16C:
You have to set the global interrupt enable bit upon function entry to any
ISR if you want it to be interruptible.

The M16C , when it gets an interrupt request, jumps to the vector which
contains the jump to the ISR address.
The return address and the FLAG register is stored on the stack.
At the same time the I flag is cleared by hardware and: -- only after RETI
the FLG register is restored.

Thus, for every ISR that you want to have interrupted (or cascaded) by a
higher priority ISR you will have to set the global interrupt enable flag as
one of the first instructions in the ISR.

regards
/jan


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