quadrature encoder interface

On the IBM PC, I've done it both by rapid I/O sampling and a state machine as well as using devices like the HCTL-2016 decoder chip. With a micro, I'd just use the sate machine -- that darned 2016 is too-blasted expensive.

I've not seen or used one, though it should be dirt easy to make such a beast from a tiny PIC, AVR, or MSP.

Yeah. I've got some really nice optical encoder knobs with quad outputs I'll be using for instrumentation. I'll probably be back coding up the software for these. Maybe I should put it out as freeware after I'm done, if there isn't already something out there. Probably need some specs, though, if I'm going to make it generally useful.

Have you looked at the HCTL-2016, yet? It's not I2C, but it can be easily hooked up with enough I/O pins available.

Jon

The AT89C52 (et al) with Up/Dn via CLK and DIRN pins can connect directly to a qudarature encoder, if you do not mind working at one change per full cycle.

To get full cycles, you can use a ATF16V8 to condition ALE, to give

4 counts per Quad cycle, still using the T2 CLK.DIRN pins. This will work to a peak clock of > 1MHz.

Other solutions are SW, but these need care on possible edge chatter, and if they ever miss an edge, can give errors. If it is only driving a menu (etc), that has user-feedback, such errors are probably tolerable. If is part of a machine/positioning control system, you probably need higher standards.

Not that I have seen.

-jg

As a couple of others have already mentioned, if the application is of the non-critical human-in-the-loop variety (volume control, screen brightness, etc.) then a state machine run from a slow clock (100 ms or so) is lightweight and pretty simple to implement.

For higher performance applications, then something like the LS7166 may be in order

A bit pricey but handles the signal conditioning and supports fast counting.

--
Rich Webb   Norfolk, VA

"Steve at fivetrees" a écrit dans le message de news: snipped-for-privacy@nildram.net...

If you are looking for a quadrature encoder interface as part of a man-machine interface, have a look here :

Friendly yours, Robert

If you don't want to use a full-fledged quadrature encoder board or device, and if software sampling is too slow for you, then an intermediate solution is to use two garden-variety counters in your micro. Using a high-frequency clock, 4 D-flipflops, 3 XORs, and 4 NORs, you can convert A and B phase quadrature signals to UP counts and DOWN counts. Connects the UP counts to one general-purpose counter and the DOWN coutns to another such counter. Then any time you want to know the count, just read both counters (on the fly) and subract the readings. The result will be the same as if you had a quadrature encoder board.

-Robert Scott Ypsilanti, Michigan (Reply through this forum, not by direct e-mail to me, as automatic reply address is fake.)

Noted; thanks!

Steve

Understood - presumably the HF clock is to provide a degree of noise immunity on the A/B lines. I've considered such an approach, but am currently tempted by two devices which combine digital filtering, decoding, and counters: - HCTL-2016 (Agilent) - LS7166 (US Digital)

Both seem to be available, comparably priced, and in stock here in the UK; and either looks like it would do nicely. Any idea if either (or both) of these is nearing end-of-life?

Steve

The HF clock serves more than just a noise filter. It is essential in transforming a quadrature state transition into a pulse with a rising an falling edge. But the more sophisticated quadrature readers do use additional flip-flops to form a digital noise filter. The discrete gate method that I described actually takes up quite a few packages, so if you can use either of the two LSI devices that you mentioned above, then by all means use them.

-Robert Scott Ypsilanti, Michigan (Reply through this forum, not by direct e-mail to me, as automatic reply address is fake.)

This will fit into a ATF16V8BQL SPLD, so you can choose the custom chip solution, or a SPLD + 89C52 (CLK.DRIN), or use Robert's suggestion of two general UP counters (broadens the MCU choice), with separate UpClk and DnClk, which would do for moderate speeds.

-jg

Another idea would be to deploy something like a dsPIC30F2010 ? Similar price/package, but you have a choice of how 'smart' you want to make the quadrature counter...

-jg

I have a dual 8/12 bit quadrature counter design that fits in a small CPLD and has a parallel or SPI interface. Each counter can be up to 12 bits in a XC9572XL = $2.00. This has input digital filtering and a delta-count design . This means reading a channel clears the count of that channel so that keeping a larger software counter up-to-date is just a matter of adding the latest delta to the software maintained counter.

This is an all synchronous design and requires an external clock.

If you are interested I can send you the code (a little too big to post)

Peter Wallace

a

that

Thanks a great deal - I'll pass for now, but I'll keep it in mind for next time.

(Note to self: time for a refresh on CPLDs etc...)

Steve