Priority among T0 & T1

As among T0 & T1 , T0 has got higher priority than T1 , if both are calle at the same time , T0 starts executing first . But internally how does th control go back to T1 . I tried this in Keil in the debug mode and foun that the after RETI of T0 control goes to the main prog and then returns t T1. Can somebody put some more light on this ? Thanks in advance.

Reply to
CB_Rajesh
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Some clue as to WTF you are talking about would be helpful if you are expecting a helpful answer in return.

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Richard.
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Reply to
FreeRTOS.org

I am sorry CB_Rajesh, I do not answer questions from gmail accounts.

I delete all mail from gmail accounts, if FreeRTOS had'nt answered you first, I would have never seen your original post.

So please get a real email account so I can answer your 8051 timer interrupt question.

donald

PS: Its in the return address.

Reply to
donald

Hi CB_Rajesh

"CB_Rajesh" escribió en el mensaje news:g8Odnc5q5qFts_DVnZ2dnUVZ snipped-for-privacy@giganews.com...

I assume you're talking about the 8051 microcontroller here. You're right if T0 and T1 have the same priority value, but remember you can alter an ISR priority with the interrupt priority register.

That's exactly what the manual says.

The microcontroller does *not* service pending interrupts when executing the RETI instruction.

This has been used in the past to create a "single-step" execution feature with a debugger/monitor installed as an ISR that does *not* clear the interrupt flag. When the ISR (the debugger) finishes (with a RETI instruction) the execution flow goes backs to the main program for a single instruction and then returns to the ISR again (remember the interrupt flag has not been cleared inside the ISR).

This can only be used with interrupt flags that are *not* automatically cleared when the associated ISR is entered. Reading the manual, this applies to the serial port ISR only in the standard 8051 model.

Best regards Paco ================================================================ Francisco Rodriguez Ballester ( snipped-for-privacy@disca.upv.es) Postal address: Dept. DISCA, ETS Informatica Aplicada, 1N-5 Universidad Politecnica de Valencia c/Camino de Vera s/n, E-46022, Valencia (Spain) tlf: +(34) 96 387 70 07 ext. 85704 - fax: +(34) 96 387 75 79 ================================================================

Reply to
Francisco Rodriguez

q5qFts_DVnZ2dnUVZ snipped-for-privacy@giganews.com...

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Thanks all for your help .. The info had been really helpful ! ! !

Reply to
cb.rajesh.in

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