Hello,
I'm trying to disable "Critical-word first" loads for cache loads. That is, when the cache is performing a cache refill, it first loads the target data from memory, then loads the remaining words in the cacheline from memory--all as part of a burst transaction. I'm looking for a way to disable this type of cache fill. Instead, I would like the cache to load the cacheline starting from the base address of the cacheline. Any one tried this before? The reference guide claims that the PLB memory controller can send back the data in the order it desires
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page 146). However, in reality, when my PLB slave pcore sends back the data in order of ascending addresses, the processor assumes that I sent it back the target data first, so it uses the wrong word.
Thanks,
NN