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PLL and noise questions

Hey gurus,

I'm trying to understand how PLLs work, so I have some (basic?) questions...

  1. When a PLL has "locked" to an incoming siqnalg, is the phase error between the output signal and the input signal 0 deg/radians or is the phase offset just fixed?

i.e. Assuming PLL lock condition, if I have the input to a PLL up on a scope and I bring the output up on a scope, will the rising and falling edges of both waveforms be aligned up, or will I see some offset between rising(and falling) of input and output?

  1. Related to above: If the phase error is fixed and non-zero, is there any way (with PLLs/DPLLs or DLL?) to time-align the waveforms so they are close to perfectly in phase?

  1. If I understand correctly, PLLs can track phase variations AND frequency variations (dTheta/dT) just by adjusting a VCO(with a control- loop)?

  2. I was looking at specs for noise and I see it's specified in

nano-Volts/(square_root(Frequency)) along with another units, dBFS.

Is there any article or website, or section of a book that actually explains these units, how they came about and how they're used? I have several engineering books, but I don't ever see discussion of noise, especially with those units.

And no, this isn't for homework!

-- With warm regards

Jay.

Reply to
Jay
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There are many kinds of PLLs and each kind has a different locked condition. They are generally classified by the type of phase detector used. If the phase detector is the type that produces a fixed voltage for a fixed phase error, then the PLL will lock with a static offset sufficient to maintain the required control voltage to the VCO. If the phase detector is the type that integrates the phase error, then even a small phase error will eventually accumulate the required integral of VCO feedback voltage, so that kind of PLL will lock with zero phase error.

-Robert Scott Ypsilanti, Michigan (Reply through newsgroups, not by direct e-mail, as automatic reply address is fake.)

Reply to
Robert Scott

The classic 4046 in nearly any CMOS series has detectors for both types. The multiplier (xor) detector locks at 90 degrees and the digital detector locks at zero. It's an easy thin to start with.

HTH

Tauno Voipio tauno voipio @ iki fi

Reply to
Tauno Voipio

The phase is usually 90degrees or pi/2, as only then the two signals multiplied are zero.

The phase error is assumed zero when the signals are 90degrees to each other. Yes, there is some timing to lock involved and it is dependent on the loop gain function.

Yes.

There are various application notes from eg Analog Devices and others. The noise of a PLL is called phase noise and is also expressed as 'ps Jitter RMS'.

Rene

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Reply to
Rene Tschaggelar

Take a look at th HMC439 and 440 Phase freq detector data sheet and the PLL calculator on Hittite Microwaves website http:

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Reply to
maxfoo

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