Pipelining in microcontrolers

koles wrote in news:cmr71m$7dm$ snipped-for-privacy@panorama.wcss.wroc.pl:

Are the PICs pipelined? If so, how many stages? In general, if the CPU is pipelined you can usually get some benefit from the load and branch delay slots.

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Reply to
Mark A. Odell
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Hi,

Do you have any documents of the pipelining or of the pipelining in microcontrolers (i'm interesting PIC microcontroler) ??

thank's a lot

Reply to
koles

Please define "project."

Reply to
Guy Macon

Yes, it's PIC 16C5X

If so, how many stages? There is two stages, first fetch, and the second is execution. All instructions are single cycle, except for any program branches.

In general, if the CPU is

I have to project more efficient pipelining for this microcontroller, and I have a lot of questions :)

Can You help me ?

bye, thanks

Reply to
armad

What do you mean by "more efficient"? Generally, the point of pipelining is to speed up execution by making each step simple enough to be performed more quickly than the larger step. This comes at a price of increasing complexity. As you add more stages, you run into the possibility that a following instruction attempts to use the result of an earlier step that is still in process. Accommodating that increases the design complexity and also makes the timing dependent on register dependencies.

One of the advantages of simple processors, such as the PIC, is that the execution time is very simple to determine -- each instruction requires a fixed number of cycles. Once you pipeline deeply enough to have dependencies, the model gets more complex. Add in caching and it gets much worse, in terms of determining exact timing. Those techniques are used for more complex, fast processors, but is a hindrance for many applications using the simple processors.

Thad

Reply to
Thad Smith

Like most RISC microcontrollers, I think that the Microchip PIC family has a three-stage pipeline: fetch, execute, store.

If you are really interested, I suggest that you get yourself a PIC software simulator, and examine the execution cycles for assembly language instructions strung together so you can figure it out yourself, O.K.?

-Bill Giovino

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Reply to
Bill Giovino

The Microchip PIC midrange reference manual explains the Q-states fairly completely, IIRC.

Best regards, Spehro Pefhany

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Reply to
Spehro Pefhany

When I saw "project", I'd like to say suggest. So I have to suggest better pipelining for PIC microcontroller. I can add more registers to microcontroller, to stores result from specific cycles. I'm searching documents about this, bo I founded nothing. I'm still searching...

thanks

Reply to
koles

ups ... but I found nothing...

Reply to
armad

Guy Mac>

When you make this suggestion, do you have any reason to believe that anyone will listen to your suggestion? Know any IC designers?

The PIC has a certain performance at a certain price that many users like. If you don't like that price/performance point, there are a wide variety of other parts you can use, ranging from 4-bit chips will suited for watches/calculators to the latest from AMD or Intel.

Adding registers has nothing to do with pipelining. I suggest that you start with studying pipelining in processors starting with the

80486 and working your way to the latest AMD/Intel offerings.
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Guy Macon
Reply to
Guy Macon

Ah. Nothing wrong with asking for homework help. I suggest posting the exact questions the teacher wishes you to answer. Nobody will spoonfeed the answers to you, but many people will help you find where to look for answers.

Reply to
Guy Macon

I know, I know :) but I have to do it on my studies :(

Reply to
koles

The problem with pipelining is how to feed new computations at every available cycle to keep the pipeline saturated. Having a large number of independent registers as source end destination operands will make it possible to keep the pipeline saturated by parallel operations, until the pipeline is stalled only sometimes in the future, when an operation needs the result of a previous pending operation.

This is how many (all?) RISC processors are designed, by maximising the number of register to register operations executed and minimising the number of memory reference operations executed (which would stall the pipeline due to slower memory access and/or due to risk of memory access conflicts).

The Z80 would be interesting to implement with a pipelined ALU, since the Z80 has two independent register sets, which could feed the pipelined ALU in parallel in a multithreaded application. That would be a very simple form of hyperthreading :-).

Paul

Reply to
Paul Keinanen

IIRC it's fetch/input/compute/output with four instructions in the pipe at any moment. The 17C... portion of the reference manual described this best, back when I needed to know.

Regards. Mel.

Reply to
Mel Wilson

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