PHY Configuration

I have been using an emac core to be implemented as standalone in an FPGA. I was successful in implementing the core, but failed in PHY layer.

Im using an SMSC MII 83C185 chip and i have been trying to configure it through an MDIO interface which i seperately implemented (not the one comes with the core). I have clocked the MDC at 1Mhz(specifications tell it to be no greater then 2.5Mhz). And i have been trying to write the registers for PHY configuration. In this regard i failed even though i have not found any timing mismatch between signals.

So i tried to crack down the problem. I tried a working processor core implementation for ethernet in a starter kit and i tried to read the MDC clock and MDIO data. To my surprise i have not found a single state change in the MDC pin (no clock) and MDIO data itself is held at low all the time.I have seen the specs and found that the operating mode configuration pins brought outside the chip are left floating(the chip is not hardware configured)

Doesn't the PHY require to be configured through MDIO interface before data transfer..? How can this be possible..? Is there any other way to configure the PHY other than fixed hardware and MDIO software configuration..?

regards knight

In article , knight wrote: [ ... ]

Clearly something's not right. Most PHY datasheets are pretty clear about MDC/MDIO timing and structure. Did you send a proper preamble? Are you sure the PHY is at the address you're emitting? Did you emit the start pulse correctly?

[ snip ]

No, actually, most PHYs don't *require* configuration - they can be almost always be strapped to come up in the right mode for the board design. If the PHY can't be strapped to the mode the board needs, consider a different PHY.

Depends on the PHY. Some have MDIO/MDC interfaces as the only choice, others have small parallel buses (8 or 16 bit wide), some use I2C, I don't think I've seen one that used MPI, but there's probably one or two out there.

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