Hello,
I needed to get ideas on how to simulate a FIFO interface on the PCI interface. I have a SBC w/ vxWorks and a Communication board in a cPCI chassis. The SBC runs an application that feeds data through the PCI interface to a FIFO on the Comm board. The Comm board has a number of control and status registers and receives data through a single 32-bit memory mapped address (that is the interface to the FIFO on the board). I am not allowed to make any modifications to the application running on the SBC.
For the Comm simulator, I was thinking of using another SBC and ?somehow? configure some of its memory to be setup to respond to the address range for the Comm board. Maybe using shared memory. I could write a program for this SBC to read the memory mapped registers and react to what is being written. I would then ?somehow? get an interrupt whenever any of this memory mapped registers where written to. It would be important to respond quickly, especially for the one register interface to the FIFO. The concern is whether the ISR that copies the data to a buffer be fast enough to simulate the FIFO interface?
Has anybody done this already? Can somebody shed light on the ?somehow?s? that I have? Any other ideas on how to do this simulation?
Javier