PC104-FPGA newbie questions

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Hello - I'm venturing into a PC104 project and have few questions to
start off. I have no experience with PC104 whatsoever.

The goal is for a PC104 module to talk to another board with an FPGA on
it. Questions are:

1. Can I use any version of Linux on the PC104 ?

2. To save time, I hope to use the PC104 in 8-bit mode. Does anyone see
a problem with this approach ?

3. Does anyone have experience writing verilog on the FPGA to talk to a
PC104 ? I hope CLK, Addr, Data are all that's critical. What other
complexities should I envision ?

4. I presume the Linux driver on the PC104 can issue outb() & inb()
equivalent calls to send/receive data to/from the FPGA. Is this correct
?

Thanks.


Re: PC104-FPGA newbie questions
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I guess you mean a PC/104 board with an x86-compatible CPU.  PC/104 is just
a form factor.  Yes, you can use any version of Linux, provided you have a
harddisk or flash module large enough to hold the Linux distribution.


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No.  8-bit is the the easiest and slowest mode.  An 8-bit in or out
instruction takes ~1.5 usec.


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For an I/O-mapped FPGA, you can use SA0-9, SD0-7, /IOR, /IOW and AEN.  The
I/O cycles you see are not synchronous to any clock in a well-defined
manner.  When SA0-9 match and AEN and /IOR are low, you have a read cycle,
and output the data on SD0-7.  When SA0-9 match, AEN is low, and there is a
rising edge on /IOW, you have a write cycle, and latch the data on SD0-7.


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Yes.

Karl Olsen



Re: PC104-FPGA newbie questions
Thanks Karl. Most helpful. Quick follow-up question.

When you say "For an I/O-mapped FPGA ... ", what is the effort involved
? Should something special be done on the FPGA to make it an I/O mapped
FPGA ? Should I be wiring the M/IO# pin on the PC/104 somehow ?

I don't understand how the OS would interpret an external device as an
I/O mapped device.

Thanks again.


Re: PC104-FPGA newbie questions
Another question on the same topic:

I'm looking at the Linux source for an ISA driver and I see it uses
"request_region()" call to get an address range for the device. For
this call to succeed, are there any requirements from the FPGA ?

How will the FPGA know that it is being addressed ? (Since its the only
device on the PC/104 bus, I guess all signals are being addressed to
it. But I'm curious as to know whether there should be any hardware
setup needed to make the FPGA respond to a specific address range.)

Thanks.


Re: PC104-FPGA newbie questions

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No, this only to ensure that the kernel doesn't try to use the same
addresses for different devices.


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All signals in the PC/104 bus run in parallel.  There is no automatic
address assignment in PC/104.  You simply pick an address range (possibly
configurable by jumpers etc.) that nobody else uses.  I/O range 3F8h-3FFh is
normally used by COM1, 2F8h-2FFh by COM2, and so on.  It is your
responsibility to pick an unused range.  Ranges like 200h-21Fh, 220h-23F,
300h-31Fh, 320h-33Fh are normally good candidates.  In your FPGA, you then
look at SA0-9, and when they match the agreed-upon range, you have a cycle
for you.

Karl Olsen



Re: PC104-FPGA newbie questions

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There is no M/IO# pin in the PC/104 bus.  Making an I/O mapped device
involves no more than the SA, SD, IOR#, IOW# and AEN stuff I described.  The
PC/104 bus is the same as the old ISA bus, and it is not that complex.


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Simply by issuing inb() and outb() instructions to the relevant addresses.

Karl Olsen



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