Hi,
I have read about paging, segmentation and paged segmentation and I believe I have (nearly) understood how these techniques are implemented in hardware. However, I am till confused about the some details which I'll highly appreciated your assistance on.
1- When using pure paging and for a page size equal to 4KB=2^12, each page should be located at 4KB's offset in the main memory. There is no similar restriction with segmentation since segments don't have a pre-set size. What about paged segmentation? Should segments be located at 2^12 boundaries since each segment now is a set of pages [assume page size is equal to 2^12].2- How can we as users choose any of the above techniques, is there any register to set by the compiler (or the linker, loader)?
3- From what I read segmentation requires the use of the assembly indirect addressing, while each address contains two fields [register segment: offset]. If we are in real mode, register segment content [after probably right shift] determines the starting address of the segment in the main memory and the offset field represents the offset within the segment in the physical memory. However, if we are using protected mode, the content of the register segment points to a segment table which includes the starting address of the segment. Am I right?4- Now regarding protected mode/real mode. Are they part of the CPU modes which defines the execution mode? How are they related to user mode and kernel mode?
5- Is the segment table part of the CPU architecture?6- Who set the values of the segment registers and the segment table? I presume the kernel. Does the kernel decide on behalf of the user which INDEX VALUE the code/stack/data/ etc segment is given and set the content of the segment table entries [including in particular the starting address of the segment in the main memory and its size] accordingly? I presume the segment table content should be saved/updated each time a segment is relocated?
7- Sometimes I encounter while using my computer, system messages [like protection errors] showing a similar address to OFFF:XXXX which indicates a very high number of segments in an application , a highly unlikely situation as the number of segments in an application tends to be moderately small. So what 0FFF stands for and why it is as high?8- Actually, how the CPU differentiates between the next 3 instructions [in protected mode]: Load 3, CS:XXX Load 3, DS:XXX Load 3, SS:XXX
Will each of the above instructions be translated to a different numerical code depending of the type of segment?
If this is case why not skip this "unnecessary" step by binding permanently each segment register to a fixed entry in the segment table? May be this has not been done because an application might have a large number of segments than the available cpu segments registers. As such a particular register will be used for more than one segment and its content should be used to index the segment table. Am I right?
9- The last question about pure segmentation. You can see from the figure available at this linkI understand that in paper we have to find the segment index and offset by splitting the address(0x43) into two fields. However why the address is considered as only one field instead of two fields. Will the CPU appends CS content to XXXX while it encounters an instruction similar to load 3, CS:XXXX
Many thanks for your help and sorry for the long message
Regards