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p2020 - explanation of ddr parameters in boot_format config?

Hi,

I'm debugging the p2020 based system. When building the u-boot loader, it is essential to provide good DDR parameters in the boot_format configuration file. Unfortunately I can't find any description of those parameters neither in

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nor in p2020 manuals. Does anybody know where those parameters are described and how to suit them to particular DDR chips and memory layout?

-- TIA, WZab

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wzab
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Analyzing the sample boot_format configuration provided with the boot_format sources I have found, that probably the 0xff702nnn followed by 32 bit word describes writing of this 2nd word to the nnn register in DDR controller. However other commands are still unclear for me :-(.

-- WZab

Reply to
wzab

Using the above theory, I have analysed setups included in

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In setup config_ddr3_1gb_p1_p2_rdb_pc_800M.dat we have 088:ff702000 CS0_BNDS 08c:0000003f What agrees with fig 8-2 and Table 8-6 of P2020RM.pdf

In setup config_ddr3_2gb_p1_p2_rdb_pc_800M.dat we have: 088:ff702000 CS0_BNDS 08c:0000003f and later: 0f8:ff702008 CS1_BNDS 0fc:0040007f

However, what is unclear, is the setup config_ddr2_1g_p1020rdb_533M.dat In which we find: 88:ff702000 CS0_BNDS 8c:0000001f

If this board contains also 1GB of memory, why the CS0_BNDS is set to cover only 512MB?

Reply to
wzab

[...]

OK. I've missed the configuration of DDR_SDRAM_CFG register: in config_ddr2_1g_p1020rdb_533M.dat we have:

80:ff702110 84:43080000 DBW=3D00 (64-bit bus)

while in config_ddr3_1gb_p1_p2_rdb_pc_800M.dat we have:

080:ff702110 084:470c0008 DBW=3D01 (32-bit bus)
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wzab

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