Oscillator and Corruption of Registers

In a dynamic processor, the register contents are stored in very small capacitors, very much like DRAM

Unless these registers are refreshed within a certain time, the charges will slowly leak away, and corrupt the data.

Your point makes sense if correlated with something like DRAM.

But, how does it play a role with a normal processor ?

Here Dynamic processor is defined as below (It is a normal Processor with few special features w.r.t Operating Frequency) - 'If the minimum operating frequency of a processor is specified to be greater than zero, then that processor is said to have dynamic operation (Hence called as Dynamic Processor).'

Karthik Balaguru

What part of the statement is ambiguous?

In a dynamic processor (ie. one that cannot live if its clock is stopped), the registers are essentially DRAM cells. If they don't get refreshed, they decay. How much margin you have there to under-clock the device depends on the individual chip production variations, temperature, voltage, etc etc.

Do you mean to say that the register contents are stored in very small capacitors like DRAM in a Processor ? (DRAM may need to be refreshed thousands of times per second) But, that should making the Processor slow :(:( What do you think ?

There are many varities of DRAM . What kind of DRAM can possibly be present inside the processor for storing the register contents ? Any ideas ?

Karthik Balaguru

Interesting :):)

Karthik Balaguru

It doesn't necessarily make the processor slow. It just requires special consideration in the implementation.

As long as registers are updated during the normal flow of instructions, they will be automatically refreshed every cycle or every couple of cycles. For registers that need to keep the same contents, you just add an extra path from the register back to itself, so that the old contents will be written again.

The many varieties of DRAM are mostly with regards to the external interface. The internal design of the single DRAM cell does not vary much. It's basically a single transistor and some capacitance.

There were two typical architectures for that purpose: two phase and four phase.

The last dynamic CPU probably was the original i8080. Since then all general purpose CPU designs were static.

The underclocking margin on the modern CPUs is governed by the operational limits of the internal PLL.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

The registers are made of a type of memory that needs to be refreshed periodically.

That is true of a dynamic processor. A static processor works the way you describe.

IIRC the 8080 (and z80) was static. It could be halted without harm.

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 Chuck F (cbfalconer at maineline dot net)
   
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Montgomery Scott was suspended in a transporter buffer for over 75 years, due to a power failure,

Martin

The Z80 and possibly 8085 could have been static, but at least the TI variant of 8080 (TMS8080) specified 2 us maximum clock cycle time. Also the 8080 clock driver (8224) had high CPU clock drive capability (typically required by a dynamic construction). Also MC6800 needed quite high two phase clock drive capability and the clock frequency range was specified as 0.1-1 MHz, also suggesting a dynamic construction.

One of the sales arguments for the CMOS RCA 1802 was that it was fully static and the clock could be stopped or manually single stepped. This would suggest that many competitors did not have this capability at that time-

Paul

It is not impossible that my memory is faulty. I know I could halt my systems at any point at any time. However, it might have been continuous application of the wait signal.

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 Chuck F (cbfalconer at maineline dot net)
   
   Try the download section.

You couldn't stop a CPU clock, at least for the original i8080. However there used to be many remakes of i8080 which were full static. Some even could run on the single +5V supply, whereas the original 8080 required +/-5 and +12. AFAIK the original Z80 was static, however there was a limit for the maximum duration of the clock in low. Power dissipation?

BTW my favourite ~25 year old RPN calculator is P-MOS dynamic 4-phase serial architecture.

Vladimir Vassilevsky DSP and Mixed Signal Consultant