Open source Logic Analyser

Craig ,

This isn't really an answer to your question about open-source hardware, rather an idea of a way to get your logic analyzer.

Consider using an FPGA.

Altera Cyclone is an excellent part for this:

The EP1C6Q240 has :

4 dedicated clock lines for sampling Loads of IO 4 IO banks, each of which can operate from different voltage levels Embedded memory arrays for waveform storage Lots of embedded logic / latches to create complex multi-state triggers Free development software

One thing that might be a pain is that it isn't directly 5v tolerant, but a few 5v tolerant low voltage buffers isn't much of an overhead.

Gary.

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Circuit Cellar INK, Issue 89, Dec. 97 "A Simple Multipurpose Logic Analyser" by Janusz Mlodzianowski

Might be a useful reference.

"The analyser consists of up to 40 TTL channels, connects to a host PC via parallel printer port and is capable of capturing data at a frequency of up to 50 MHz (external, and 16 internal frequencies). The trigger word can be set to any combination of "Low", "High" and "Don't care" states. In addition, a preset number of Triggers and samples after the final Trigger can be specified. The Logic Analyser buffer is 2048 samples wide."

Logic analysis is one of my favorite rant topics, so buckle up. What do you mean by 20-40 MHz? If you mean state analysis of a system that has states that can change every 25 ns, you have one set of problems. If you mean you want to look for timing problems on a system that changes state every 25 ns, you have a different set of problems.

If you want to do it with affordable hardware, ie hardware that's only a few times faster performance to what you're debugging, plan on pipelining your word recognizer.

A LOGIC ANALYZER IS USELESS IF YOU CAN'T TRUST IT COMPLETELY!!

Channel skew will drive you buggy. You wanna build 64 channels spread across 8 cables and keep the skew low. Getting the signal from the source without loading it and with well defined notions of 1 and 0 and without adding skew and crosstalk and, and, and is a VERY difficult problem. This was 20 years ago at Tektronix, we got to

10 MHz, just barely, by using ribbon cable with a ground plane along the whole length. The higher speed stuff used lots of twisted pairs in a round cable. Remember that typical cable is made by running one wire down the center and twisting the others around it. This is DISASTER for a logic analyzer. You need special cables.

There's an interesting technique that revolves around a FPGA. You compile the trigger recognizer state machine on the spot and download it to the FPGA. Years ago, when I approached FPGA vendors about the subject, they flatly refused to disclose how to program their parts. More recently, there's a commercial analyzer on the market that appears to work just that way. Don't remember the name, but they sell 'em at Fry's.

I built a probe hooked to a socket, programmed a GAL20V8 as a word recognizer and used that to trigger my scope or simple LA that had insufficient trigger capability. Was a pain to program each time, but I was able to do things I couldn't do otherwise.

I've found that most problems where you're in control of the design fit into two categories.

1) you can make indirect measurements and determine the source of the problem logically. 2) It's very complex and intermittent and even the best LA won't help you. ie debugging the innards of a CPU.

Yep, there are situations in between where a good LA will help, but as a percentage, it ain't much.

And there's always that ole chicken-egg problem. It takes a logic analyzer to debug a logic analyzer design.

I could go on for days, but I'm tired.

Bottom line: If your time has any value, go buy a used logic analyzer. Make sure it comes with probes.

If you're just in it to build one and don't really care if you can trust it, go right ahead and have fun with it. Start with the biggest FPGA that you can afford the tools to program. Choose your glue logic family from those who's 0 and 1 propagation delays are the same.

mike

--
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21' RV, 400cc Dirt Bike
Police Scanner, LCD overhead projector
Tek 2465, ham radio, 30pS pulser
Tektronix Concept Books, spot welding head...
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I had actually given the idea of an FPGA based design some thought. I would love to be able to be let loose on an FPGA, I think I've got enough VHDL & Verilog under my belt to give it a decent go.

But getting access to the synthesis tools always seems to cause issues. The "free" ones from the manufacture always seem overly crippled.

Also, this one seems to be something that I've missed along the way, how the F**k do you program the buggers once you've synthesized your design. I think that the old school PLD's from Xilinx etc used to require an external EPROM to store the binary mask in. I think the manufactures finally started providing Flash based ones but I've got no idea how you'd go about actually downloading the mask to one with out requiring some expensive programmer.

FPGA's at the moment seem too expensive, the per component cost is high, the cost of development tools is large. And the price of the development boards I've seen is some what excessive.

If I do this project I'd like to do it in such away that it affordable and accessible for almost everyone. I think that means I'm going to have to accept some loss of flexibility and stick to readily available components. I feel that 74F series components are probable the most widely available set of components suitable for the job. May be I'm wrong I'd love to hear suggestions, particularly those regarding free/low cost FPGA development tools

Craig

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More analysis of a system that can change states upto each 50ns or so. I realise that in reality I'm dreaming if i think i can pick up glitches a magnitude smaller in a system at this speed using off the self components.

agrred, and so long as you realise the limitations of your equipment I feel you should be able to trust it.

Thank you this is an area I hadn't thought about. Clearly I'm going to have to give it some more thought particuarly channel skew. Although I was under the impression that most of the twisted pair cables aroung today were of a resonable quality. Surely if I can transmit Gbs down CAT 5 even taking into account the pulse shaping to help limint the ISI then it's not unreasonable to think i can recieve 20MHz signals down a similar twisted pair with minimal cross talk problems..

Fry's.

May be a suitable alternative for me at the moment.

I don't expect a logic analyser to be a magic bullet in any circumstances. I do expect to get some time savings from it from not having to repeat the fault condition every 2 minuets in order to take another reading.

if I could i would.

Thanks for the tip.

Craig

That's a good idea - very low cost :) - these days, you'd use CPLD like Atmels ATF150x family. ISP progamming, low power, and 5V capable. Tools are free on the web.

Logic Analysers are just dual-port memory load/read, once you have the trigger qualified.

-jg

Atmel still has external eeprom type-fpgas I think. I have a few I never used.

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Altera's web edition of Quartus II software is free, and is pretty much full featured - the limitations are in devices supported (i.e not their screaming high end Stratix devices) and there are no third party synthesis/simulation tools bundled (Altera's native ones seem fine to me)

The EP1C6Q240 is around USD 24 in development quantities, and Altera have a low cost serial FLASH configuration device (don't know what low cost means in practice) that can be JTAG ISP'ed using a cheap ByteBlaster parallel cable.

I don't know about evaluation boards and device programmers - Altera's website lists Cyclone development kits down to USD 500.

I hadn't used an FPGA for 10 years, but I just completed a design with the above part and it was a breeze.

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Except no documentation...

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look under projects on avrfreaks.

also you will find a few searching on google.

for a logic analyser have a look at

I have an ant8. Works very well for circuits under 100MHz.

for fpga. may want to have a look at actel. have a flash based fpga so you don't need a eeprom or data flash to store your bitstram in.

also have a look on opencores.org

Alex

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no much help in your not in the US. Note the op's email address .au = Australia.

So what? Look at my e-mail address ( .ch ) which means Switzerland. I bought 3 scopes and 4 analyzers for me and others from e-bay.com (i.e. from the US). Ok, I had ot add ~$120 shipping but considering the fact that you then get working systems which you can trust and that you are not faced with X hours of developement time trouble etc. etc. made it very worthwile. I haven't regretted yet a single purchase yet. Ok, if the original poster does this for the fun of it and for learing without pressure of having an analyzer to complete a task etc. building his own might be the right decission - otherwise e-bay is really a good option.

Just my 2¢ though

Markus

Hi Craig, You may be interested in my old design that was published in Electronics Australia many years back:

Seriously, forget 74F series logic and go for a PLD/FPGA based design. Interface to the PC via USB. This has already been done here with the ANT-8, but it's not open source:

Bit expensive at over $300AU though.

Regards Dave :)

--------------------------- (remove the "_" from my email address to reply)

Check out Bitscope.

--

Regards
David Milne

Hi Craig, While it is possible to do a logic analyser with 74F/AC series logic, it's a logistic nightmare, and no one will be interested in building it, even if it's got supposedly "easy to get" 74 logic. Trying to do fully maskable triggering, with 8 bit busses running everywhere, skew, timing, buffering, storage/retrieval, latching, all across dozens of channels is a big pain in the ass from a PCB perspective. You'd be talking dense 4 layers boards, and the cost of those would more than offset the cost of going the PLD/FPGA solution. It would also be physically BIG, and if you were to go to a modular 8 channels per card approach, you'd have to sort out motherboard mounting, bus interfaces and many other issues. It's ugly, don't do it, you'll regret it.

Many of the FPGA/PLD vendors have free tools available, even if they are limited. Lattice and Atmel also have suitable FPGA/PLD solutions. If you have to pay much for software/hardware to do FPGA/PLD then you are going about it the wrong way. Flash devices are serial JTAG download, and you can often build your own serial cable from info available on the net. Same for the other FPGA, but they serial download into an external Flash or EEPROM device. A logic analyser is not complex, so you don't ned anything super fancy, a low level PLD will suffice, perhaps even one per 8 or 16 channels. That way you can stick to easy to use packages. External SRAM is cheap and easy, use cache RAM from old PC's, they can be had for FREE!. Using SRAM in an FPGA might seem neat, but it pushes up you FPGA complexity curve and you are looking at big QFP or BGA packages - yuk. Once again, not many enthusists are going to touch that, in fact I'd be willing to say none.

The biggest issue with logic analysers though is probing, as others have mentioned. It's complex, and there is no easy solution to it. It's a major reason why DIY logic analysers are not, and never will be popular.

Regards Dave :)

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Well I've been convinced. I think that a PLD based approach is probably a reasonable one to take. The cost of the FPGA's themselves seem to have dropped significantly since I last checked them. I'm off to start comparing the synthesis tools from a few different vendors.

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Take a look at

only US$200

Craig Rodgers wrote:

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Mark OToole
MCO Design and Consulting    Embedded Design and Development
http://www.mco-design.com    email: mco at computer dot org

Hi!

Thanks for the description. You surely pointed out a number of problems. How about this approach: put all the high-freq part of the LA into an FPGA, put a small uC/DSP by side of it, fix the whole thing up with a USB/Ethernet port and stuff the whole thing into the box of the POD of a usual LA. The cable length would be < 10cm (4 inches) in that case, the channel number whould be 8-9, but definitely under 16. More of these could be connected to a PC and be grouped into a wider virtual analizer. Triggering over multiple PODs like this would be hard though...

Regards, Andras Tantos