New ARM plus Mega Gate FPGA Platform

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APS has released its new APS-ArmXF FPGA Rapid Development Platform

The APS-ArmXF Rapid Development Platform is a highly programmable
FPGA and ARM development system used for product development, product
implementation,  and algorithm testing, just to mention a few. The
system includes one ARM-Block and up to 3 XF-Blocks along with
software and ARM  C, VHDL, and LINUX example code and templates.


Each ARM-Block contains A 166 MHz 32 bit ARM Processor, with 32 MB of
High speed SDRAM, 8MB of on board flash, an IDE Compact Flash
interface to allow up to 1GB of storage space. The ARM-Block also
contains a large number IO options including SERIAL, SPI, TCP/IP, and
USB ports. THE ARM-Block exists as the main support, configuration,
and control interface to the large programmable logic XF-Blocks. The
ARM-Block interfaces to up to 3 XF-Blocks via a fast 16 bit IO
interface bus.  Having the ARM processor existing outside of the FPGA
blocks leaves 100% of the large FPGAs logic in the XF-Blocks
available for user designs. The fact that an ARM processor exists in
the system does not preclude the system from being used for embedded
processor design in the FPGAs them selves in the XF-Blocks. In fact
the XF-Block architecture is set up rather well for FPGA embedded
processor design as well as Digital Signal Processing. The ARM-Blocks
also can load and run the complete development system for the ARM-
Block. The system is shipped with a preloaded LINUX kernel and a
complete GNU development tool chain.


Each XF-Block in the system contains a large million gate FPGA,
optional  256K by 18 ZBT SRAM, three oscillator sockets, XC9572 CPLD,
optional on board programmable Direct Digital Synthesized (DDS)
clock, Phase Lock Loop Clock Multiplier chip, and 2 RS232
transceivers, along with up to 166 IO pins. The system's small size
makes it great for embedded designs where a powerful programmable
logic device is required. Up to three XF-Blocks can be stacked onto
one ARM-Block to yield a modular 3 Million gate stack with 3 CPLD
arrays, up to 3 separate DDS clock modules up to 3 256K x 18 ZBT SRAM
modules (12 Mbits ) up to six separate oscillator sockets, 6 XF-Block
serial port transceivers, 3 PLL clock multiplier chips, and up to 498
IO connections. The XF-Block stack's modularity works well for
separating design task assignments. Each engineer can design and test
his/her portion of the design separately in their own XF-Block

The APS-ArmXF web page is

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