Need help with SPI interface in 8051

Hello everybody,

My F022 acts as the SPI master.I have the register R7 whose value changes from time to time. Every time its value changes, I need F022 to transfer one 8 bit value to the slave followed by the 8 bit value of R7.

How can I do this in ASM

I have tried doing this as follows: mov spi0cn,#003h mov spi0cfg,#007h clr fpga_cs_1 mov spi0dat,#11h wait_here1: jnb spi0cn.7,wait_here1 clr spi0cn.7 setb fpga_cs_1 clr fpga_cs_1 mov spi0dat,R7 wait_here2: jnb spi0cn.7,wait_here2 clr spi0cn.7 setb fpga_cs_1 ret

I am not sure if this is doing it right..

Any ideas or suggestions about this?

Thank you,

Methi

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methi
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Hello,

My SPI is intialized as follows:

mov p0mdout,#015h ( port configuration)

mov spi0cn,#003h ;SPI Control Register mov spi0cfg,#007h ;SPI Configuration Register mov spi0ckr,#063h ;SPI Clock Rate Register

My sysmtem clk is intialized as follows:

mov oscxcn,#067h ;External Oscillator Control Register clr a ; osc djnz acc,$ ; wait for djnz acc,$ ; at least 1ms

ox_wait: mov a,oscxcn jnb acc.7,ox_wait ;poll XTLVLD

mov oscicn,#008h ;Internal Oscillator Control Register

As far as I know, these are initialized correctly

So there should be an SCK output at P0.2...but there isnt

I dont understand where i am goin wrong..

Any help is greatly appreciated..

Thank you,

Methi methi wrote:

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methi

Hello everybody, My F022 acts as the SPI master.I have the register h5 whose value changes from time to time. Every time its value changes, I need F022 to transfer one 8 bit value(03h) to the slave followed by the 8 bit value of h5.

My code for doing that is as follows:

Its a subroutine which is called everytime the value of h5 changes

fpga_talk: clr fpga_cs_1 (select the slave) mov spi0dat,#003h ( move 03h and start the transfer) wait_here1: jnb spi0cn.7,wait_here1 (wait till transfer is completed) clr spi0cn.7 (clear the bit) mov r7,spi0dat (move the data sent by the slave to R7) lcall delay_spi (call a small delay for 1ms) mov spi0dat,h5 (move the h5 value and start the transfer) wait_here2: jnb spi0cn.7,wait_here2 clr spi0cn.7 mov r7,spi0dat setb fpga_cs_1 (de-select the slave) ret (return from subroutine)

My SPI is intialized as follows:

mov p0mdout,#015h ( port configuration)

mov spi0cn,#003h ;SPI Control Register mov spi0cfg,#007h ;SPI Configuration Register mov spi0ckr,#063h ;SPI Clock Rate Register

My sysmtem clk is intialized as follows:

mov oscxcn,#067h ;External Oscillator Control Register clr a ; osc djnz acc,$ ; wait for djnz acc,$ ; at least 1ms

ox_wait: mov a,oscxcn jnb acc.7,ox_wait ;poll XTLVLD

mov oscicn,#008h ;Internal Oscillator Control Register

As far as I know, these are initialized correctly

My XBRx registers are as follows:

mov xbr0,#006h ;XBAR0: Initial Reset Value mov xbr1,#014h ;XBAR1: Initial Reset Value mov xbr2,#040h ;XBAR2: Initial Reset Value

My XBARE bit is set to '1' which means that SPI is enabled.

On going through the examples in one of the application notes of Cygnals:AN128, I have noticed the following:

The XBR0 register is initialized with the value:

XBR0 = 0x0F; // skip SPI pins in XBAR

Should I be doing the same?

And also I havent connected the NSS pin ( pin 57 which is P0.5 to my slave)

What I am right now seeing is that my master ( F022) is sending the 2 bytes of data ( 03h,01h) for 16 clock cycles.

01h is the first value h5 takes.

And then it sends 00h,00h for the next 16 clock cycles.

This is again followed by 03h,01h for the enxt 16 clock cycles.

I dont want this to happen.I just want it to transfer it once.

Also another problem is that when the value of h5 changes, I am calling the subroutine again for another transfer...

I notice that even though its the same subroutine, there is no sck or anything happening

Any ideas...

Thankyou, Methi

Any help is greatly appreciated..

Reply to
methi

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