I have a question for any PowerQuicc II gurus out there. We are currently starting an embedded project using the 8247 running at a 66MHz external clock.
We are planning on using FCC1 and FCC2 for 100 Base T ethernet, and SMC1 & SMC2 to implent two 9600 baud UARTs. This is a simple porting effort from an 8260 based design and is not expected to be a big deal. We are using vxWorks Tornado 5.5 as the real time OS. We will be supporting the ethernet and rs232 using real vxWorks drivers. We are expecting fairly heavy traffic on FCC1. FCC2 should be lightly loaded and the traffic on the SMC1, and 2 will be neglible.
We also have a need to program up to 6 FPGAs. The FPGAs are on daughter boards that are hot swappable. They are Spartan 3 FPGAs from Xilinx. We have decided to use Xilinx's serial slave mode to program the FPGA. This mode requires a PROGRAM output signal, a DONE and INIT input signals, DATA and CLOCK output. We are not planning on writing real vxWorks drivers for the FPGA programming.
The program binary that is to be sent to the FPGA is 7.8 megabits in size. The FPGA limits the clock rate to 6MHz. There is a requirement that we program the FPGA in under 5 seconds. Using a clock of 6MHz gives us a best case program time of 1.3 seconds well under the limit.
We are considering a scheme where we preload the FPGA binary into SDRAM. We have 64MBytes, this will use about 1 MByte. The PowerQuicc II Family Reference manual says on page 20-1 that the SCC can be run at up to 1/4 of the system clock. So it seems like we should be able to configure one of the Baud Rate Generators for 6 MHz and use one of the SCC in synchronous mode and run the TxD and BRxO signal to the FPGA.
Does anyone see any major obstacles to the described implementation? Would an interface other than the SCC be more appropriate. Eager to here suggestions, counter suggestions, or positive negative experiences if relavant. Thanks. In this application we are