mux / serdes design

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Dear newsgroup readers,

I am currently working on a multiplexer design in VHDL. For the time being
the design should run on a Xilinx Virtex II FPGA but actually I am not
concerned about any target device later on. My question is more general.
What I want to do is multiplex four input signals into one output signal,
meaning that there are four parallel inputs that should merge into one
serial output. Therefore the output must be four times faster than the
input, right? I see problems in generating the faster clock out of the
master clock of the slower inputs, that means I HAVE TO provide the fast
clock for the serial output right away and then transform it back to the
slower to handle the input, is that right?
What's more I want to multiplex the signals byte-wise. How can that be
achieved WITHOUT wasting a great amount of registers? And how to manage the
data being transfered between the two clock domains?

Regards, Leroy

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