My design has 2 PicoBlaze processors on a Spartan-IIE sharing a common IO bus (PORT_ID, IN_PORT, OUT_PORT, READ_STROBE, WRITE_STROBE). I am planning to use simple priority based bus arbitration. Now I am trying to figure out the minimal changes I need make to the PicoBlaze core in order for the IO logic to be bus aware. It needs to assert BREQ to request the bus, wait until BACK, use the bus, then deassert BREQ to release the bus.
Any suggestions are most appreciated. Any resources I can look at?
Thanks,
- Abdul